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| resources:quick-start:ad5791 [12 Feb 2013 16:56] – [Features] Estibaliz Sanz | resources:quick-start:ad5791 [16 Apr 2013 16:18] (current) – text edits throughout Yuet Ng |
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| ====== AD5781/AD5791 Quick Start Guide ====== | ====== AD5781/AD5791 Quick Start Guide ====== |
| ** Single, 18-/20-Bit, Voltage Output DACs, SPI Interface ** | ** Single, 18-/20-Bit, Voltage Output DACs, SPI Interface ** |
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| <WRAP CENTERALIGN>{{ :resources:quick-start:ad5781_ad5791_functional_block_diagram.png?direct&400 |}}</WRAP> | |
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| <WRAP CENTERALIGN>//Figure 1. Functional Block Diagram//</WRAP> | |
| <WRAP clear></WRAP> | |
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| ===== Features ===== | ===== Features ===== |
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| * High relative accuracy (INL): ±0.5 LSB maximum (18-bit [[adi>ad5781|AD5781]]) | * High relative accuracy (INL): ±0.5 LSB maximum (18-bit [[adi>ad5781|AD5781]]) |
| * 1ppm resolution, 1ppm INL (20-bit [[adi>ad5791|AD5791]]) | * 1 ppm resolution, 1 ppm INL (20-bit [[adi>ad5791|AD5791]]) |
| * 7.5 nV/√Hz output noise spectral density | * 7.5 nV/√Hz output noise spectral density |
| * 0.19 LSB long-term linearity error stability (20-bit [[adi>ad5791|AD5791]]) | * 0.19 LSB long-term linearity error stability (20-bit [[adi>ad5791|AD5791]]) |
| * Operating temperature range: −40°C to +125°C | * Operating temperature range: −40°C to +125°C |
| * 20-lead TSSOP package | * 20-lead TSSOP package |
| * Wide power supply range up to ±16.5 V | * Wide power supply range of up to ±16.5 V |
| * 35 MHz Schmitt triggered digital interface | * 35 MHz Schmitt triggered digital interface |
| * 1.8 V compatible digital interface | * 1.8 V compatible digital interface |
| | |
| | ===== Functional Block Diagram ===== |
| | {{ :resources:quick-start:ad5781_ad5791_block_diagram.png?direct&500 |}} |
| | <WRAP CENTERALIGN>//Figure 1. //</WRAP> |
| | <WRAP clear></WRAP> |
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| ===== Pin Configurations ===== | ===== Pin Configuration ===== |
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| <WRAP CENTERALIGN>{{ :resources:quick-start:ad5781_ad5791_pin_configuration.png?direct&300 |}}</WRAP> | <WRAP CENTERALIGN>{{ :resources:quick-start:ad5781_ad5791_pin_configuration.png?direct&300 |}}</WRAP> |
| \\ | <WRAP CENTERALIGN>//Figure 2. 20-Lead TSSOP Pin Configuration// </WRAP> |
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| <WRAP CENTERALIGN>//Figure 2. 24-Lead LFCSP// </WRAP> | |
| <WRAP clear></WRAP> | <WRAP clear></WRAP> |
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| ^ Mnemonic ^ Description ^ | ^ Mnemonic ^ Description ^ |
| |INV | Inverting Input Connection for External Amplifier.| | |INV | Inverting input connection for external amplifier.| |
| |V<sub>OUT</sub> | Analog output voltage. | | |V<sub>OUT</sub> | Analog output voltage. | |
| |V<sub>REFPS</sub> | Positive Reference Sense Voltage Input. Connect a voltage in the range of 5V to V<sub>DD</sub> - 2.5V. | | |V<sub>REFPS</sub> | Positive reference sense voltage input. Connect a voltage in the range of 5 V to V<sub>DD</sub> - 2.5 V. | |
| |V<sub>REFPF</sub> | Positive Reference Force Voltage Input. Connect a voltage in the range of 5V to V<sub>DD</sub> - 2.5V. | | |V<sub>REFPF</sub> | Positive reference force voltage input. Connect a voltage in the range of 5 V to V<sub>DD</sub> - 2.5 V. | |
| |V<sub>DD</sub> | Positive Analog Supply Connection. Connect a voltage in the range of 7.5V to 16.5V. V<sub>DD</sub> must be decoupled to AGND. | | |V<sub>DD</sub> | Positive analog supply connection. Connect a voltage in the range of 7.5 V to 16.5 V. V<sub>DD</sub> must be decoupled to AGND. | |
| |<m>overline{RESET}</m> | Active Low Reset. Asserting this pin returns the DAC to its power-on status. | | |<m>overline{RESET}</m> | Active low reset. Asserting this pin returns the DAC to its power-on status. | |
| |<m>overline{CLEAR}</m> | Active Low Input. Asserting this pin sets the DAC register to a user defined value and updates the DAC output. | | |<m>overline{CLR}</m> | Active low input. Asserting this pin sets the DAC register to a user defined value and updates the DAC output. | |
| |<m>overline{LDAC}</m> | Active Low Load DAC Logic Input. This is used to update the DAC register and, consequently, the analog output. | | |<m>overline{LDAC}</m> | Active low load DAC logic input. This is used to update the DAC register and, consequently, the analog output. | |
| |V<sub>CC</sub> | Digital Supply. Connect a voltage in the range of 2.7V to 5.5V. V<sub>CC</sub> should be decoupled to DGND. | | |V<sub>CC</sub> | Digital supply. Connect a voltage in the range of 2.7 V to 5.5 V. V<sub>CC</sub> must be decoupled to DGND. | |
| |IOV<sub>CC</sub> | Digital Interface Supply. Voltage range is from 1.71V to 5.5V. | | |IOV<sub>CC</sub> | Digital interface supply. Voltage range is from 1.71 V to 5.5 V. | |
| |SDO |Serial Data Output.| | |SDO |Serial data output.| |
| |SDIN | Serial Data Input. | | |SDIN | Serial data input. | |
| |SCLK | Serial Clock Input. Data can be transferred at clock rates of up to 35 MHz. | | |SCLK | Serial clock input. Data can be transferred at clock rates of up to 35 MHz. | |
| |<m>overline{SYNC}</m> | Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data. | | |<m>overline{SYNC}</m> | Active low digital interface synchronization input. This is the frame synchronization signal for the input data. | |
| |DGND | Ground Reference Pin for Digital Circuitry. | | |DGND | Ground reference for digital circuitry. | |
| |V<sub>REFNF</sub> | Negative Reference Force Voltage Input. Connect a voltage in the range of V<sub>SS</sub> + 2.5V to 0V. | | |V<sub>REFNF</sub> | Negative reference force voltage input. Connect a voltage in the range of V<sub>SS</sub> + 2.5 V to 0 V. | |
| |V<sub>REFNS</sub> | Negative Reference Sense Voltage Input. Connect a voltage in the range of V<sub>SS</sub> + 2.5V to 0V. | | |V<sub>REFNS</sub> | Negative reference sense voltage input. Connect a voltage in the range of V<sub>SS</sub> + 2.5 V to 0 V. | |
| |V<sub>SS</sub> | Negative Analog Supply Connection. Connect a voltage in the range of -16.5V to -2.5V. V<sub>SS</sub> must be decoupled to AGND. | | |V<sub>SS</sub> | Negative analog supply connection. Connect a voltage in the range of -16.5 V to -2.5 V. V<sub>SS</sub> must be decoupled to AGND. | |
| |AGND | Ground Reference Pin for Digital Circuitry. | | |AGND | Ground reference for analog circuitry. | |
| |R<sub>FB</sub> | Feedback Connection for External Amplifier. | | |R<sub>FB</sub> | Feedback connection for external amplifier. | |
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| **Table 2. Hardware Control Pins Truth Table** | **Table 2. Hardware Control Pins Truth Table** |
| ^/LDAC ^/CLR ^/RESET ^Function^ | ^/LDAC ^/CLR ^/RESET ^Function ^ |
| |X<sup>1</sup> |X<sup>1</sup> |0 |DAC in reset mode. The device cannot be programmed.| | |X<sup>1</sup> |X<sup>1</sup> |0 |DAC in reset mode. The device cannot be programmed.| |
| |X<sup>1</sup> |X<sup>1</sup> |⇑<sup>2</sup> |DAC is turned to its power-on state. All registers are set to their default values.| | |X<sup>1</sup> |X<sup>1</sup> |⇑<sup>2</sup> |DAC is returned to its power-on state. All registers are set to their default values.| |
| |0 |0 |1 |DAC register loaded with the clearcode register value and output set accordingly.| | |0 |0 |1 |DAC register loaded with the clearcode register value and output set accordingly.| |
| |0 |1 |1 |Output set according to the DAC register value.| | |0 |1 |1 |Output set according to the DAC register value.| |
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| ===== Shift Register Contents ===== | ===== Input Shift Register Contents ===== |
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| {{ :resources:quick-start:ad5781_91_shift_register_contents.png?direct&700 |}} | {{ :resources:quick-start:ad5781_91_shift_register_contents.png?direct&700 |}} |
| <WRAP CENTERALIGN>//Figure 3. Shift Register Contents [[adi>ad5791|(AD5791]])//</WRAP> | <WRAP CENTERALIGN>//Figure 3. Input Shift Register Contents //</WRAP> |
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| **Table 3. Register Address Definitions** | **Table 3. Register Address Definitions** |
| ^Read/Write^Register Address^^^ ^ | ^:::^Register Address ^^^:::^ |
| ^R/W ^C2 ^C1 ^C0 ^Description ^ | ^Read/Write (R/W)^C2 ^C1 ^C0 ^Description ^ |
| |X |0 |0 |0 |No operation| | |X<sup>1</sup> |0 |0 |0 |No operation| |
| |0 |0 |0 |1 |Write to the DAC Register| | |0 |0 |0 |1 |Write to the DAC register| |
| |0 |0 |1 |0 |Write to the Control Register| | |0 |0 |1 |0 |Write to the control register| |
| |0 |0 |1 |1 |Write to the Clearcode Register| | |0 |0 |1 |1 |Write to the clearcode register| |
| |0 |1 |0 |0 |Write to the Software Control Register | | |0 |1 |0 |0 |Write to the software control register | |
| |1 |0 |0 |1 |Read from the DAC Register | | |1 |0 |0 |1 |Read from the DAC register | |
| |1 |0 |1 |0 |Read from the Control Register| | |1 |0 |1 |0 |Read from the control register| |
| |1 |0 |1 |1 |Read from the Clearcode Register| | |1 |0 |1 |1 |Read from the clearcode register| |
| | <sup>1</sup> X = don't care. |
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| {{ :resources:quick-start:ad5781_91_control_register.png?direct&700 |}} | {{ :resources:quick-start:ad5781_91_control_register.png?direct&700 |}} |
| <WRAP CENTERALIGN>//Figure 4. Control Register [[adi>ad5791|(AD5791]])//</WRAP> | <WRAP CENTERALIGN>//Figure 4. Control Register //</WRAP> |
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| **Table 4. Control Register Functions** | **Table 4. Control Register Functions** |
| ^Bit Name ^Description^ | ^Bit Name ^Description ^^ |
| |RBUF |Output amplifier configuration control. **"0"**: Internal amplifier powered up. **"1"**: **(default)** Internal amplifier powered down.| | |RBUF |Output amplifier configuration control. || |
| |OPGND |Output ground clamp control. **"0"**: DAC output clamp to ground removed and DAC placed in normal mode. **"1"**:** (default)** DAC output clamped to ground and DAC placed in tristate mode.| | |:::|**Setting** |**Function** | |
| |DACTRI |DAC tristate control. **"0"**: DAC in normal operating mode. **"1"**: **(default)** DAC in tristate mode.| | |:::|0 |Internal amplifier powered up. | |
| |BIN/2sC |DAC register coding selection. **"0"**: **(default)** DAC register uses twos complement coding. **"1"**: DAC register uses offset binary coding.| | |:::|1 (default)|Internal amplifier powered down. | |
| |SDODIS |SDO pin enable/disable control. **"0"**: **(default)** SDO pin enabled. **"1"**: SDO pin disabled (tristate).| | |OPGND |Output ground clamp control. || |
| |LIN COMP |Linearity error compensation for varying reference input spans. **"0000"**: **(default)** reference input span up to 10 V. **"1001"**: Reference input span between 10 V and 12 V. **"1010"**: Reference input span between 12 V and 16 V. **"1011"**: Reference input span between 16 V and 19 V. **"1100"**: Reference input span between 19 V and 20 V. | | |:::|**Setting** |**Function** | |
| |R/<m>overline{W}</m> |Read/write select bit. **"0"**: [[adi>ad5790|(AD5790]]) addressed for a write operation. **"1"**: [[adi>ad5790|(AD5790]]) addressed for a read operation. | | |:::|0 |DAC output clamp to ground removed and DAC placed in normal mode. | |
| | |:::|1 (default) |DAC output clamped to ground and DAC placed in tristate mode. | |
| | |DACTRI |DAC tristate control. || |
| | |:::|**Setting** |**Function** | |
| | |:::|0 |DAC in normal operating mode. | |
| | |:::|1 (default) |DAC in tristate mode. | |
| | |BIN/2sC |DAC register coding selection. || |
| | |:::|**Setting** |**Function** | |
| | |:::|0 (default) |DAC register uses twos complement coding. | |
| | |:::|1 |DAC register uses offset binary coding. | |
| | |SDODIS |SDO pin enable/disable control. || |
| | |:::|**Setting** |**Function** | |
| | |:::|0 (default) |SDO pin enabled. | |
| | |:::|1 |SDO pin disabled (tristate). | |
| | |LIN COMP |Linearity error compensation for varying reference input spans. Note that the reference input span options for the [[adi>ad5781|AD5781]] are: up to 10 V (0000) and 20 V (1100). See the [[adi>ad5781|AD5781]] data sheet for additional details.|| |
| | |:::|**Setting** |**Function** | |
| | |:::|0000 (default) |Reference input span up to 10 V. | |
| | |:::|1001 |Reference input span between 10 V and 12 V. | |
| | |:::|1010 |Reference input span between 12 V and 16 V. | |
| | |:::|1011 |Reference input span between 16 V and 19 V. | |
| | |:::|1100 |Reference input span between 19 V and 20 V. | |
| | |R/<m>overline{W}</m> |Read/write select bit. || |
| | |:::|**Setting** |**Function** | |
| | |:::|0 |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a write operation. | |
| | |:::|1 |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a read operation. | |
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| {{ :resources:quick-start:ad5781_91_software_control_register.png?direct&700 |}} | {{ :resources:quick-start:ad5781_91_software_control_register.png?direct&700 |}} |
| <WRAP CENTERALIGN>//Figure 5. Software Control Register [[adi>ad5791|(AD5791]])//</WRAP> | <WRAP CENTERALIGN>//Figure 5. Software Control Register //</WRAP> |
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| **Table 5. Software Control Register Functions** | **Table 5. Software Control Register Functions** |
| ^Bit Name ^Description^ | ^Bit Name ^Description ^ |
| |LDAC<sup>2</sup> |Setting this bit to 1 updates the DAC register and consequently the DAC output.| | |LDAC<sup>1</sup> |Setting this bit to 1 updates the DAC register and, consequently, the DAC output.| |
| |CLR<sup>1</sup> |Setting this bit to 1 sets the DAC register to a user defined value and updates the DAC output.| | |CLR<sup>2</sup> |Setting this bit to 1 sets the DAC register to a user defined value and updates the DAC output.| |
| |RESET |Setting this bit to 1 returns the [[adi>ad5790|(AD5790]]) to its power-on state.| | |RESET |Setting this bit to 1 returns the [[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] to its power-on state.| |
| \\ | <sup>1</sup> The LDAC function has no effect when the <m>overline{CLR}</m> pin is low. Refer to Table 2 in the [[resources/quick-start/ad5791#hardware_control_pins_truth_table|Hardware Control Pins Truth Table]] section for additional details.\\ |
| <sup>1</sup> The CLR function has no effect when the <m>overline{LDAC}</m> pin is low. Refer to the Hardware Control Pins Truth Table for further detail. | <sup>2</sup> The CLR function has no effect when the <m>overline{LDAC}</m> pin is low. Refer to Table 2 in the [[resources/quick-start/ad5791#hardware_control_pins_truth_table|Hardware Control Pins Truth Table]] section for additional details. |
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| <sup>2</sup> The LDAC function has no effect when the <m>overline{CLR}</m> pin is low. Refer to the Hardware Control Pins Truth Table for further detail. | |
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| where:\\ | where:\\ |
| //V<sub>REFN</sub>// is the negative voltage applied at the V<sub>REFN</sub> input pin. \\ | //V<sub>REFN</sub>// is the negative voltage applied at the V<sub>REFNx</sub> input pin. \\ |
| //V<sub>REFP</sub>// is the positive voltage applied at the V<sub>REFP</sub> input pin. \\ | //V<sub>REFP</sub>// is the positive voltage applied at the V<sub>REFPx</sub> input pin. \\ |
| //D// is the decimal equivalent. \\ | //D// is the 18-bit ([[adi>ad5781|AD5781]]) or 20-bit ([[adi>ad5791|AD5791]]) code programmed to the DAC. \\ |
| //N// is the number of bits. \\ | //N// is the number of bits. \\ |
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| ===== Example 1: Initializing and writing to the DAC Register ===== | ===== Example 1: Initializing and Writing to the DAC Register ===== |
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| === Initializing the DAC === | === Initializing the DAC === |
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| To initialize the part, | To initialize the part, |
| - Remove the DAC output clamp to ground and place the DAC in normal operating mode (**OPGND = "0"**, **DACTRI = "0"**). | * Because this initialization is a write to the part, set the R/<m>overline{W}</m> bit to a Logic 0. |
| - As this initializing is a write to the part, **R/W** bit should be a logic **"0"**. | * Keep the default mode for LIN COMP, SDODIS, and RBUF. |
| - To write in binary coding select **BIN/2sC = "1"**. | * To write in binary coding, select BIN/2sC = 1. |
| - Keep the default mode for RBUF, SDODIS and LIN COMP: | * Set DACTRI = 0 and OPGND = 0 to place the DAC in normal operating mode and remove the DAC output clamp to ground, respectively. |
| * The internal amplifier powered down (**RBUF = "1"**) | |
| * The SDO pin enabled for future readings from the part (**SDODIS = "0"**) | |
| * Linearity error compensation for a reference input span up to 10V. (**LIN COMP = "0000"**) | |
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| Write the following over the serial interface: 0010 0000 0000 0000 0001 0010 (Read/Write bit, three register address bits, 20 data bits). | |
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| </WRAP> | Write the following over the serial interface: 0010 0000 0000 0000 0001 0010 (R/<m>overline{W}</m> bit, three register address bits, 20 data bits). |
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| <WRAP important> | |
| To write in binary coding select **BIN/2sC = "1"**. | |
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| | See Table 6 and Figure 6. |
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| The default coding is the offset binary, the same 24-bit data will impact in a different way depending on the coding selected. The user will need to ensure the coding used by writing to the control register or reading back from it. | \\ |
| </WRAP> | **Table 6. Bit Settings to Initialize and Write to the Part** |
| | ^Bit(s) ^Bit Name ^Setting ^Description ^ |
| | |23 |R/<m>overline{W}</m> |0 |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a write operation | |
| | |[22:20] |C2, C1, C0 |010 |Write to the control register | |
| | |[9:6] |LIN COMP |0000 |Linearity error compensation for a reference input span up to 10 V | |
| | |5 |SDODIS |0 |The SDO pin enabled for future readings from the part | |
| | |4 |BIN/2sC |1 |Offset binary coding | |
| | |3 |DACTRI |0 | Place the DAC in normal operating mode | |
| | |2 |OPGND |0 | Remove the DAC output clamp to ground | |
| | |1 |RBUF | 1 |Internal amplifier powered down | |
| |
| | <WRAP center round important 60%> |
| | To write in offset binary coding, set BIN/2sC = 1. |
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| | The default coding is twos complement. The same 24-bit data impacts the values that the user writes to or reads from the part in a different way depending on the coding selected. The user must verify the coding used by writing to the control register or reading back from it. |
| | </WRAP> |
| | </WRAP> |
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| {{ :resources:quick-start:example1_step1_ad5781_91.png?direct&700 |}} | {{ :resources:quick-start:example1_step1_ad5781_91.png?direct&700 |}} |
| <WRAP CENTERALIGN>//Figure 6. Initializing the part//</WRAP> | <WRAP CENTERALIGN>//Figure 6. Initializing the Part//</WRAP> |
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| === Writing to the DAC Register === | === Writing to the DAC Register === |
| <WRAP tip>To write a midscale code to the DAC register, select the write option from the read/write bit (**R/W = "0"**), the correspondent register address (**C2C1C0 = "001"**) and the data bits for a midscale code. | <WRAP tip>To write a midscale code to the DAC register, |
| | * Set R/<m>overline{W}</m> = 0 to select the write option from the read/write bit. |
| | * Set C[2:0] = 001 for the correspondent register address. |
| | * Set D[19:0], the data bits, for a midscale code. |
| | The 24-bit data to write over the serial interface is as follows: |
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| The 24-bit data to write over the serial interface is: | 18-bit [[adi>ad5781|AD5781]]: 0001 1000 0000 0000 0000 00XX |
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| | 20-bit [[adi>ad5791|AD5791]]: 0001 1000 0000 0000 0000 0000 |
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| 18-bit **AD5781**: 0001 1000 0000 0000 0000 00XX | |
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| 20-bit **AD5791**: 0001 1000 0000 0000 0000 0000 | where X = don't care. |
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| | \\ |
| | See Table 7 and Figure 7. |
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| | **Table 7. Bit Settings to Write to DAC Register** |
| | ^Bit(s) ^Bit Name ^Setting ^Description ^ |
| | |23 |R/<m>overline{W}</m> |0 |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a write operation | |
| | |[22:20] |C2, C1, C0 |001 |Write to the DAC register | |
| </WRAP> | </WRAP> |
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| {{ :resources:quick-start:example1_step2_ad5781_91.png?direct&700 |}} | {{ :resources:quick-start:example1_step2_ad5781_91.png?direct&700 |}} |
| <WRAP CENTERALIGN>//Figure 7. Write to the DAC Register)//</WRAP> | <WRAP CENTERALIGN>//Figure 7. Writing to the DAC Register//</WRAP> |
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| ===== Example 2: Clear the DAC to a defined value ===== | ===== Example 2: Clearing the DAC to a Defined Value ===== |
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| === Writing to the Clearcode Register === | === Writing to the Clearcode Register === |
| <WRAP tip>To define the value at which the DAC output is set when the CLR pin or CLR bit in the software control register is asserted, write the desired code to the clearcode register. | <WRAP tip>To define the value at which the DAC output is set when the <m>overline{CLR}</m> pin or CLR bit in the software control register is asserted, write the desired code to the clearcode register. |
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| For a full scale clear code, write the following over the serial interface: | For a full-scale clear code, write the following over the serial interface: |
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| 18-bit **AD5781**: 0011 1111 1111 1111 1111 11XX | 18-bit [[adi>ad5781|AD5781]]: 0011 1111 1111 1111 1111 11XX |
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| | 20-bit [[adi>ad5791|AD5791]]: 0011 1111 1111 1111 1111 1111 |
| | \\ |
| | \\ |
| | where X = don't care. |
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| | \\ |
| | See Figure 8. |
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| 20-bit **AD5791**: 0011 1111 1111 1111 1111 1111 | |
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| </WRAP> | </WRAP> |
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| {{ :resources:quick-start:example2_step1_ad5781_91.png?direct&700 |}} | {{ :resources:quick-start:example2_step1_ad5781_91.png?direct&700 |}} |
| <WRAP CENTERALIGN>//Figure 8. Write Full Scale code to the Clearcode Register//</WRAP> | <WRAP CENTERALIGN>//Figure 8. Writing Full-Scale Code to the Clearcode Register//</WRAP> |
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| === Writting to the Software Control Register === | === Writing to the Software Control Register === |
| <WRAP tip>To set the DAC register to a user defined value and update the DAC output set the CLR bit to a logic **"1"**. | <WRAP tip>Set the CLR bit to a Logic 1 to set the DAC register to a user defined value and update the DAC output. |
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| The user should see the DAC output value change to full scale code. | The user should see the DAC output value change to full-scale code. |
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| | \\ |
| | See Figure 9. |
| </WRAP> | </WRAP> |
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| {{ :resources:quick-start:example2_step2_ad5781_91.png?direct&700 |}} | {{ :resources:quick-start:example2_step2_ad5781_91.png?direct&700 |}} |
| <WRAP CENTERALIGN>//Figure 9. Clear the part to a user defined value//</WRAP> | <WRAP CENTERALIGN>//Figure 9. Clearing the Part to a User Defined Value//</WRAP> |
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| | === Reading From the Clearcode Register === |
| | <WRAP tip>To confirm the clearcode value written to the part, read the data from the clearcode register (full scale for this example). |
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| | Write the following over the serial interface: |
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| | 1011 XXXX XXXX XXXX XXXX XXXX |
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| | \\ |
| | where X = don't care. |
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| | \\ |
| | See Figure 10. |
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| === Readback the Clearcode Register === | |
| <WRAP tip>To confirm the clearcode value written to the part, read the data on the clearcode register (Full scale for this example). Write the following over the serial interface: 1011 XXXX XXXX XXXX XXXX XXXX. | |
| <WRAP center round important 60%> | <WRAP center round important 60%> |
| Remember that this action is a read function, so the R/<m>overline{W}</m> bit is set to **"1"**. | Note that this action is a read function. Therefore, set the R/<m>overline{W}</m> bit = 1. |
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| The data bits are **don't care**, as the aim is to read from the part and not a write function. | D19 to D0, the data bits, are don't care bits because the intention is to read from the part, and not to write to the part. |
| </WRAP> | </WRAP> |
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| {{ :resources:quick-start:example2_step3_ad5781_91.png?direct&700 |}} | {{ :resources:quick-start:example2_step3_ad5781_91.png?direct&700 |}} |
| <WRAP CENTERALIGN>//Figure 10. Readback from the clearcode register//</WRAP> | <WRAP CENTERALIGN>//Figure 10. Reading from the Clearcode Register//</WRAP> |
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