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====== AD5781/AD5791 Quick Start Guide ======
** Single, 18-/20-Bit, Voltage Output DACs, SPI Interface **
===== Features =====
  * High relative accuracy (INL): ±0.5 LSB maximum (18-bit [[adi>ad5781|AD5781]])
  * 1 ppm resolution, 1 ppm INL (20-bit [[adi>ad5791|AD5791]])
  * 7.5 nV/√Hz output noise spectral density
  * 0.19 LSB long-term linearity error stability (20-bit [[adi>ad5791|AD5791]])
  * <0.05 ppm/°C temperature drift 
  * 1 μs output voltage settling time
  * 1.4 nV-sec midscale glitch impulse
  * Operating temperature range: −40°C to +125°C
  * 20-lead TSSOP package
  * Wide power supply range of up to ±16.5 V
  * 35 MHz Schmitt triggered digital interface
  * 1.8 V compatible digital interface

===== Functional Block Diagram =====
{{ :resources:quick-start:ad5781_ad5791_block_diagram.png?direct&500 |}}
<WRAP CENTERALIGN>//Figure 1. //</WRAP>
<WRAP clear></WRAP>
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===== Pin Configuration =====
<WRAP CENTERALIGN>{{ :resources:quick-start:ad5781_ad5791_pin_configuration.png?direct&300 |}}</WRAP>
<WRAP CENTERALIGN>//Figure 2. 20-Lead TSSOP Pin Configuration// </WRAP>
<WRAP clear></WRAP>
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**Table 1. Function Descriptions for Quick Start**
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^   Mnemonic           ^ Description                    ^ 
|INV                      | Inverting input connection for external amplifier.|
|V<sub>OUT</sub>          | Analog output voltage.         |
|V<sub>REFPS</sub>         | Positive reference sense voltage input. Connect a voltage in the range of 5 V to V<sub>DD</sub> - 2.5 V.    |
|V<sub>REFPF</sub>         | Positive reference force voltage input. Connect a voltage in the range of 5 V to V<sub>DD</sub> - 2.5 V.    |
|V<sub>DD</sub>           | Positive analog supply connection. Connect a voltage in the range of 7.5 V to 16.5 V. V<sub>DD</sub> must be decoupled to AGND.    |
|<m>overline{RESET}</m> | Active low reset. Asserting this pin returns the DAC to its power-on status.   |
|<m>overline{CLR}</m> | Active low input. Asserting this pin sets the DAC register to a user defined value and updates the DAC output.    |
|<m>overline{LDAC}</m> | Active low load DAC logic input. This is used to update the DAC register and, consequently, the analog output.   |
|V<sub>CC</sub>          | Digital supply. Connect a voltage in the range of 2.7 V to 5.5 V. V<sub>CC</sub> must be decoupled to DGND.    |
|IOV<sub>CC</sub>          | Digital interface supply. Voltage range is from 1.71 V to 5.5 V.    |
|SDO                       |Serial data output.|
|SDIN                      | Serial data input.  |
|SCLK                  | Serial clock input. Data can be transferred at clock rates of up to 35 MHz.   |
|<m>overline{SYNC}</m> | Active low digital interface synchronization input. This is the frame synchronization signal for the input data.   |
|DGND                  | Ground reference for digital circuitry.   |
|V<sub>REFNF</sub>         | Negative reference force voltage input. Connect a voltage in the range of V<sub>SS</sub> + 2.5 V to 0 V.    |
|V<sub>REFNS</sub>         | Negative reference sense voltage input. Connect a voltage in the range of V<sub>SS</sub> + 2.5 V to 0 V.    |
|V<sub>SS</sub>   | Negative analog supply connection. Connect a voltage in the range of -16.5 V to -2.5 V. V<sub>SS</sub> must be decoupled to AGND. |
|AGND    | Ground reference for analog circuitry.  |
|R<sub>FB</sub>         | Feedback connection for external amplifier.    |


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===== Hardware Control Pins Truth Table =====
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**Table 2. Hardware Control Pins Truth Table**
^/LDAC                ^/CLR                ^/RESET                ^Function  ^
|X<sup>1</sup>        |X<sup>1</sup>	   |0		          |DAC in reset mode. The device cannot be programmed.|
|X<sup>1</sup>        |X<sup>1</sup>	   |⇑<sup>2</sup>		          |DAC is returned to its power-on state. All registers are set to their default values.|
|0                    |0	           |1		          |DAC register loaded with the clearcode register value and output set accordingly.|
|0                    |1	           |1		          |Output set according to the DAC register value.|
|1                    |0                   |1                     |DAC register loaded with the clearcode register value and output set accordingly. |
|⇓<sup>3</sup>        |1	           |1		          |Output set according to the DAC register value. |
|⇓<sup>3</sup>        |0	           |1	                  |Output remains at the clearcode register value.|
|⇑<sup>2</sup>        |1	           |1	                  |Output remains set according to the DAC register value.|
|⇑<sup>2</sup>        |0	           |1	                  |Output remains at the clearcode register value.|
|1                    |⇓<sup>3</sup>	   |1	                  |DAC register loaded with the clearcode register value and output set accordingly.|
|0                    |⇓<sup>3</sup>	   |1	                  |DAC register loaded with the clearcode register value and output set accordingly.|
|1                    |⇑<sup>2</sup>	   |1	                  |Output remains at the clearcode register value.|
|0                    |⇑<sup>2</sup>	   |1	                  |Output set according to the DAC register value.|

<sup>1</sup> X is don't care.
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<sup>2</sup> ⇑ is rising edge.
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<sup>3</sup> ⇓ is falling edge.
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===== Input Shift Register Contents =====

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{{ :resources:quick-start:ad5781_91_shift_register_contents.png?direct&700 |}}
<WRAP CENTERALIGN>//Figure 3. Input Shift Register Contents //</WRAP>

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**Table 3. Register Address Definitions**
^:::^Register Address ^^^:::^
^Read/Write (R/W)^C2	^C1	^C0	^Description  ^
|X<sup>1</sup>    |0	|0	|0	|No operation|
|0    |0	|0	|1	|Write to the DAC register|
|0    |0	|1	|0	|Write to the control register|
|0    |0	|1	|1	|Write to the clearcode register|
|0    |1        |0      |0      |Write to the software control register |
|1    |0	|0	|1	|Read from the DAC register |
|1    |0	|1	|0	|Read from the control register|
|1    |0	|1	|1	|Read from the clearcode register|
<sup>1</sup> X = don't care.
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====Control Register====

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{{ :resources:quick-start:ad5781_91_control_register.png?direct&700 |}}
<WRAP CENTERALIGN>//Figure 4. Control Register //</WRAP>
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**Table 4. Control Register Functions**
^Bit Name            ^Description  ^^
|RBUF                |Output amplifier configuration control.  ||
|:::|**Setting**  |**Function**  |
|:::|0  |Internal amplifier powered up.  |
|:::|1 (default)|Internal amplifier powered down. |           
|OPGND               |Output ground clamp control. ||
|:::|**Setting**  |**Function**  |
|:::|0  |DAC output clamp to ground removed and DAC placed in normal mode.  |
|:::|1 (default)  |DAC output clamped to ground and DAC placed in tristate mode. |
|DACTRI              |DAC tristate control. ||
|:::|**Setting**  |**Function**  |
|:::|0  |DAC in normal operating mode. |
|:::|1 (default)  |DAC in tristate mode.  |
|BIN/2sC             |DAC register coding selection.  ||
|:::|**Setting**  |**Function**  |
|:::|0 (default)  |DAC register uses twos complement coding. |
|:::|1  |DAC register uses offset binary coding. |
|SDODIS              |SDO pin enable/disable control. ||
|:::|**Setting**  |**Function**  |
|:::|0 (default)  |SDO pin enabled.  |
|:::|1  |SDO pin disabled (tristate).  |
|LIN COMP            |Linearity error compensation for varying reference input spans. Note that the reference input span options for the [[adi>ad5781|AD5781]] are: up to 10 V (0000) and 20 V (1100). See the [[adi>ad5781|AD5781]] data sheet for additional details.||
|:::|**Setting**  |**Function**  |
|:::|0000 (default)  |Reference input span up to 10 V. |
|:::|1001  |Reference input span between 10 V and 12 V.  |
|:::|1010  |Reference input span between 12 V and 16 V.  |
|:::|1011  |Reference input span between 16 V and 19 V.  |
|:::|1100  |Reference input span between 19 V and 20 V.  |
|R/<m>overline{W}</m>       |Read/write select bit.  ||
|:::|**Setting**  |**Function**  |
|:::|0  |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a write operation.  |
|:::|1  |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a read operation.  |
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====Software Control Register====

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{{ :resources:quick-start:ad5781_91_software_control_register.png?direct&700 |}}
<WRAP CENTERALIGN>//Figure 5. Software Control Register //</WRAP>
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**Table 5. Software Control Register Functions**
^Bit Name            ^Description  ^
|LDAC<sup>1</sup>                |Setting this bit to 1 updates the DAC register and, consequently, the DAC output.|            
|CLR<sup>2</sup>               |Setting this bit to 1 sets the DAC register to a user defined value and updates the DAC output.|
|RESET               |Setting this bit to 1 returns the [[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] to its power-on state.|
<sup>1</sup> The LDAC function has no effect when the <m>overline{CLR}</m> pin is low. Refer to Table 2 in the [[resources/quick-start/ad5791#hardware_control_pins_truth_table|Hardware Control Pins Truth Table]] section for additional details.\\
<sup>2</sup> The CLR function has no effect when the <m>overline{LDAC}</m> pin is low. Refer to Table 2 in the [[resources/quick-start/ad5791#hardware_control_pins_truth_table|Hardware Control Pins Truth Table]] section for additional details.

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===== Transfer Function =====
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 <m>V_OUT = (V_REFP - V_REFN) * D/(2^N-1) + V_REFN</m>\\
\\
where:\\ 
//V<sub>REFN</sub>// is the negative voltage applied at the V<sub>REFNx</sub> input pin. \\
//V<sub>REFP</sub>// is the positive voltage applied at the V<sub>REFPx</sub> input pin. \\
//D// is the 18-bit ([[adi>ad5781|AD5781]]) or 20-bit ([[adi>ad5791|AD5791]]) code programmed to the DAC. \\ 
//N// is the number of bits. \\ 
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===== Example 1: Initializing and Writing to the DAC Register =====
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=== Initializing the DAC ===
<WRAP tip>

 To initialize the part, 
  * Because this initialization is a write to the part, set the R/<m>overline{W}</m> bit to a Logic 0.
  * Keep the default mode for LIN COMP, SDODIS, and RBUF.
  * To write in binary coding, select BIN/2sC = 1.
  * Set DACTRI = 0 and OPGND = 0  to place the DAC in normal operating mode and remove the DAC output clamp to ground, respectively. 

Write the following over the serial interface: 0010 0000 0000 0000 0001 0010 (R/<m>overline{W}</m> bit, three register address bits, 20 data bits).
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See Table 6 and Figure 6.
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**Table 6. Bit Settings to Initialize and Write to the Part**
^Bit(s)  ^Bit Name  ^Setting  ^Description  ^
|23  |R/<m>overline{W}</m>  |0  |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a write operation  |
|[22:20]  |C2, C1, C0  |010  |Write to the control register  |
|[9:6]  |LIN COMP  |0000  |Linearity error compensation for a reference input span up to 10 V |
|5  |SDODIS  |0  |The SDO pin enabled for future readings from the part |
|4  |BIN/2sC  |1  |Offset binary coding |
|3  |DACTRI  |0  | Place the DAC in normal operating mode |
|2  |OPGND  |0  | Remove the DAC output clamp to ground  |
|1  |RBUF  | 1  |Internal amplifier powered down  |

<WRAP center round important 60%>
To write in offset binary coding, set BIN/2sC = 1. 
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The default coding is twos complement. The same 24-bit data impacts the values that the user writes to or reads from the part in a different way depending on the coding selected. The user must verify the coding used by writing to the control register or reading  back from it.
</WRAP>
</WRAP>  
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\\

{{ :resources:quick-start:example1_step1_ad5781_91.png?direct&700 |}}
<WRAP CENTERALIGN>//Figure 6. Initializing the Part//</WRAP>
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=== Writing to the DAC Register ===
<WRAP tip>To write a midscale code to the DAC register, 
  * Set R/<m>overline{W}</m> = 0 to select the write option from the read/write bit. 
  * Set C[2:0] = 001 for the correspondent register address.
  * Set D[19:0], the data bits, for a midscale code.
The 24-bit data to write over the serial interface is as follows:
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18-bit [[adi>ad5781|AD5781]]: 0001 1000 0000 0000 0000 00XX
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20-bit [[adi>ad5791|AD5791]]: 0001 1000 0000 0000 0000 0000
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where X = don't care.
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See Table 7 and Figure 7. 
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**Table 7. Bit Settings to Write to DAC Register**
^Bit(s)  ^Bit Name  ^Setting  ^Description  ^
|23  |R/<m>overline{W}</m>  |0  |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a write operation  |
|[22:20]  |C2, C1, C0  |001  |Write to the DAC register  |
</WRAP>
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{{ :resources:quick-start:example1_step2_ad5781_91.png?direct&700 |}}
<WRAP CENTERALIGN>//Figure 7. Writing to the DAC Register//</WRAP>
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===== Example 2: Clearing the DAC to a Defined Value =====
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=== Writing to the Clearcode Register ===
<WRAP tip>To define the value at which the DAC output is set when the <m>overline{CLR}</m> pin or CLR bit in the software control register is asserted, write the desired code to the clearcode register. 
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For a full-scale clear code, write the following over the serial interface: 
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18-bit [[adi>ad5781|AD5781]]: 0011 1111 1111 1111 1111 11XX
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20-bit [[adi>ad5791|AD5791]]: 0011 1111 1111 1111 1111 1111
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\\
where X = don't care. 
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See Figure 8.
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</WRAP>
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{{ :resources:quick-start:example2_step1_ad5781_91.png?direct&700 |}}
<WRAP CENTERALIGN>//Figure 8. Writing Full-Scale Code to the Clearcode Register//</WRAP>
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=== Writing to the Software Control Register ===
<WRAP tip>Set the CLR bit to a Logic 1 to set the DAC register to a user defined value and update the DAC output. 
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Write the following over the serial interface: 0100 0000 0000 0000 0000 0010 
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The user should see the DAC output value change to full-scale code.
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See Figure 9.
</WRAP>
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{{ :resources:quick-start:example2_step2_ad5781_91.png?direct&700 |}}
<WRAP CENTERALIGN>//Figure 9. Clearing the Part to a User Defined Value//</WRAP>
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=== Reading From the Clearcode Register ===
<WRAP tip>To confirm the clearcode value written to the part, read the data from the clearcode register (full scale for this example). 
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Write the following over the serial interface: 
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1011 XXXX XXXX XXXX XXXX XXXX
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where X = don't care.
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See Figure 10.
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<WRAP center round important 60%>
Note that this action is a read function. Therefore, set the R/<m>overline{W}</m> bit = 1.
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D19 to D0, the data bits, are don't care bits because the intention is to read from the part, and not to write to the part.
</WRAP>

</WRAP> 
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{{ :resources:quick-start:example2_step3_ad5781_91.png?direct&700 |}}
<WRAP CENTERALIGN>//Figure 10. Reading from the Clearcode Register//</WRAP>
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