Dual, 16-/12-Bit, Voltage Output DACs with a 2 ppm/ºC Reference, SPI Interface
Figure 2. 16-Lead TSSOP
Figure 3. 16-Lead LFCSP
Table 1. Function Descriptions for Quick Start
Mnemonic | Description |
---|---|
VOUTA | Analog output voltage from DAC A. |
VOUTB | Analog output voltage from DAC B. |
NC | No connect. Do not connect to these pins. |
Connect to serial interface. | |
SCLK | Connect to serial interface. |
SDIN | Connect to serial interface. |
SDO | No connect. |
VREF | No connect. |
VDD | Connect to 5 V supply. Decouple with 10 μF and 0.1 μF capacitors. |
GND | Connect to ground. |
Tie low. | |
RSTSEL | Tie to GND to power up to zero scale. |
GAIN | Tie to GND. DAC outputs have a span from 0 V to VREF. If GAIN is tied to VLOGIC, outputs have a span of 0 V to 2 VREF. |
Tie high. | |
VLOGIC | Connect to serial interface supply voltage. |
Figure 4. Input Shift Register Contents (AD5689R)
Table 2. Command Definitions
Command | ||||
---|---|---|---|---|
C3 | C2 | C1 | C0 | Description |
0 | 0 | 0 | 0 | No operation |
0 | 0 | 0 | 1 | Write to Input Register n (dependent on |
0 | 0 | 1 | 0 | Update DAC Register n with contents of Input Register n |
0 | 0 | 1 | 1 | Write to and update DAC Channel n |
0 | 1 | 0 | 0 | Power down/power up DAC |
0 | 1 | 0 | 1 | Hardware |
0 | 1 | 1 | 0 | Software reset (power-on reset) |
0 | 1 | 1 | 1 | Internal reference setup register |
1 | 0 | 0 | 0 | Set up DCEN register (daisy-chain enable) |
1 | 0 | 0 | 1 | Set up readback register (readback enable) |
1 | 0 | 1 | 0 | Reserved |
… | … | … | … | Reserved |
1 | 1 | 1 | 1 | Reserved |
where:
D is the decimal equivalent of the binary code that is loaded to the DAC register.
N is the number of bits.
To update Channel A, write the following over the serial interface: 0001 0001 1000000000000000
(four command bits, four address bits, 16 data bits for the AD5689R).
This updates Channel A to midscale.
GAIN = 1, VOUTA = 1.25 V.
Figure 5. Simple Write—Update Channel A)