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resources:fpga:xilinx:pmod:adxl362 [03 Jan 2013 20:42] – external edit resources:fpga:xilinx:pmod:adxl362 [09 Jan 2021 00:57] (current) – user interwiki links Robin Getz
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 **HW Platform(s):**  **HW Platform(s):** 
-   * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]] +   * [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]] 
    * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]     * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]] 
-   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-ACL2|PmodACL2 (Digilent)]] \\+   * [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx|Avnet ZedBoard]] \\
  
-**System:** Microblaze, AXI, UART \\ 
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
  
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 ==== Required Hardware ==== ==== Required Hardware ====
-  * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]]+  * [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]]
   * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]     * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]  
 +  * [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx|Avnet ZedBoard]] 
   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-ACL2|PmodACL2 (Digilent)]]   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-ACL2|PmodACL2 (Digilent)]]
  
 ==== Required Software ==== ==== Required Software ====
-  * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). 
-  * A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard or 9600 for the Digilent Nexys™3 Board.+  * A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard and ZedBoard or 9600 for the Digilent Nexys™3 Board.
  
  
 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
  
-<WRAP tip>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\ +<WRAP center round tip 80%>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\ 
-If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details. +If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details.\\ 
-</WRAP>+If you are not familiar with ZedBoard and/or Xilix tools, please visit\\ [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx]] for details.</WRAP> 
 + 
 +==== Avnet LX9 MicroBoard Setup ====
  
 Extract the project from the archive file (ADXL362_<board_name>.zip) to the location you desire.  Extract the project from the archive file (ADXL362_<board_name>.zip) to the location you desire. 
  
-==== Avnet LX9 MicroBoard Setup ==== +To begin, connect the PmodACL2 to J5 connector of LX9 board (see image below). You can use an extension cable for ease of use. Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector.
- +
-To begin, connect the PmodACL2 to J5 connector of LX9 board (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board.+
  
 {{:resources:fpga:xilinx:pmod:pmodACL2.jpg?200|PmodACL2 and LX-9}} {{:resources:fpga:xilinx:pmod:pmodACL2.jpg?200|PmodACL2 and LX-9}}
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 ==== Digilent Nexys™3 Spartan-6 FPGA Board ==== ==== Digilent Nexys™3 Spartan-6 FPGA Board ====
  
-To begin, connect the PmodACL2 to JA connector of NEXYS3 board (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board.+Extract the project from the archive file (ADXL362_<board_name>.zip) to the location you desire.  
 + 
 +To begin, connect the PmodACL2 to JA connector of NEXYS3 board (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART).
  
 {{:resources:fpga:xilinx:pmod:pmodacl2_nexys3.jpg?200|PmodACL2 and Nexys™3}} {{:resources:fpga:xilinx:pmod:pmodacl2_nexys3.jpg?200|PmodACL2 and Nexys™3}}
  
-==== FPGA Configuration ====+==== Avnet ZedBoard ==== 
 + 
 +To begin, connect the PmodACL2 to JA1 connector of ZedBoard (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART). 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodacl2_zed.jpg?200|PmodACL2 and ZedBoard}} 
 + 
 +==== FPGA Configuration for Nexys3 and LX-9 MicroBoard ====
  
 Start IMPACT, and double click "Boundary Scan". Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal (set to appropiate baud rate) and then program the device using the bit file provided in the project *.zip archive, located in the "sw" folder (../adxl362/sw/ADXL362.bit). Start IMPACT, and double click "Boundary Scan". Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal (set to appropiate baud rate) and then program the device using the bit file provided in the project *.zip archive, located in the "sw" folder (../adxl362/sw/ADXL362.bit).
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 {{:resources:fpga:xilinx:pmod:PmodACL2Impact.jpg?200|Programming FPGA in IMPACT}} {{:resources:fpga:xilinx:pmod:PmodACL2Impact.jpg?200|Programming FPGA in IMPACT}}
  
-If programming was successful, the **Main Menu** will apear in your UART terminal, as seen in the picture below. There are 7 options. Pressing [1] to [5], [s] or [r] key will allow you to select the desired option.+==== FPGA Configuration for ZedBoard ==== 
 + 
 +Run the **download.bat** script from the "../bin" folder downloaded from the github (see the links in the download section of the wiki page).  
 +The script will automatically configure the ZYNQ SoC and download the *.elf file afterwards. 
 + 
 +<WRAP center round tip 80%> 
 +If the download script fails to run, modify the Xilinx Tools path in **download.bat** to match your Xilinx Installation path. 
 +</WRAP> 
 + 
 +If programming was successful, the Main Menu will apear in your UART terminal, as seen in the picture below. There are 9 options. Pressing [a], [x], [y], [z], [t], [r], [s], [i] or [m] key will allow you to select the desired option.
  
 {{:resources:fpga:xilinx:pmod:pmodacl2_menu1.jpg?600|Main Menu}}\\ {{:resources:fpga:xilinx:pmod:pmodacl2_menu1.jpg?600|Main Menu}}\\
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 {{:resources:fpga:xilinx:pmod:pmodacl2_menu8.jpg?600|Switching resolution}}\\ {{:resources:fpga:xilinx:pmod:pmodacl2_menu8.jpg?600|Switching resolution}}\\
 +
 +{{:resources:fpga:xilinx:pmod:pmodacl2_menu9.jpg?600|Switching resolution}}\\
 +
 +**Print device ID** will show information concerning the internal ID registers of ADXL362.
 +
 +{{:resources:fpga:xilinx:pmod:pmodacl2_menu10.jpg?600|Printing ID Register}}\\
  
 ===== Using the reference design ===== ===== Using the reference design =====
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 The reference design is a SPI interface used to communicate with the device. The software programs the ADXL362s internal registers, and afterwards reads desired data from the device and prints it via UART. The reference design is a SPI interface used to communicate with the device. The software programs the ADXL362s internal registers, and afterwards reads desired data from the device and prints it via UART.
  
-<WRAP important>+<WRAP round 80% important> 
 +\\
   * Connecting the PmodACL2 to the boards using an extension cable provides ease of use.   * Connecting the PmodACL2 to the boards using an extension cable provides ease of use.
-  * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard or 9600 Baud Rate for the Digilent Nexys™3 Board.+  * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard and ZedBoard or 9600 Baud Rate for the Digilent Nexys™3 Board. 
 +\\ 
 +</WRAP> 
 + 
 +<WRAP round important 80%> 
 +When using the ZedBoard reference design in order to develop your own software, please make sure that the following options are set in "system_config.h": 
 + 
 +<code c> 
 +// Select between PS7 or AXI Interface 
 +#define USE_PS7 1 
 +// SPI used in the design 
 +#define USE_SPI 1 
 +// I2C used in the design 
 +#define USE_I2C 0 
 +// Timer (+interrupts) used in the design 
 +#define USE_TIMER 0 
 +// External interrupts used in the design 
 +#define USE_EXTERNAL     0 
 +// GPIO used in the design 
 +#define USE_GPIO         0 
 +</code> 
 </WRAP> </WRAP>
  
  
 ===== Downloads ===== ===== Downloads =====
-<WRAP round download 50%> + 
-{{:resources:fpga:xilinx:pmod:adxl362_lx9.zip|Reference design source code for Avnet LX9 MicroBoard.}}\\ +<WRAP round download 80%> 
-{{:resources:fpga:xilinx:pmod:adxl362_nexys3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}}+\\ 
 +**Avnet LX-9 MicroBoard: **\\ 
 +    * {{:resources:fpga:xilinx:pmod:adxl362_lx9.zip|Reference design source code for Avnet LX9 MicroBoard.}}\\ 
 + 
 +**Digilent Nexys™3:**\\ 
 +    * {{:resources:fpga:xilinx:pmod:adxl362_nexys3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}}\\ 
 + 
 +**Avnet ZedBoard:**\\ 
 +    * [[https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_adv7511_zed|XPS Project]]\\ 
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodACL2|PmodACL2 Driver Files]]\\ 
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/Common/sw|ZYNQ SoC Peripherals Driver Files]] \\ 
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodACL2/bin|Programming Script]]\\ 
 +    
 </WRAP> </WRAP>
  
resources/fpga/xilinx/pmod/adxl362.1357242155.txt.gz · Last modified: 31 Jan 2013 09:12 (external edit)

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