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resources:fpga:xilinx:pmod:adxl362 [30 Aug 2013 14:09] – Added ZedBoard Alexandru.Tofan | resources:fpga:xilinx:pmod:adxl362 [30 Sep 2013 09:56] – links modified Alexandru.Tofan | ||
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* UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard and ZedBoard or 9600 Baud Rate for the Digilent Nexys™3 Board. | * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard and ZedBoard or 9600 Baud Rate for the Digilent Nexys™3 Board. | ||
\\ | \\ | ||
+ | </ | ||
+ | |||
+ | <WRAP round important 80%> | ||
+ | When using the ZedBoard reference design in order to develop your own software, please make sure that the following options are set in " | ||
+ | |||
+ | <code c> | ||
+ | // Select between PS7 or AXI Interface | ||
+ | #define USE_PS7 1 | ||
+ | // SPI used in the design | ||
+ | #define USE_SPI 1 | ||
+ | // I2C used in the design | ||
+ | #define USE_I2C 0 | ||
+ | // Timer (+interrupts) used in the design | ||
+ | #define USE_TIMER 0 | ||
+ | // External interrupts used in the design | ||
+ | #define USE_EXTERNAL | ||
+ | // GPIO used in the design | ||
+ | #define USE_GPIO | ||
+ | </ | ||
+ | |||
</ | </ | ||
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* [[https:// | * [[https:// | ||
* [[https:// | * [[https:// | ||
- | * [[https:// | + | * [[https:// |
* [[https:// | * [[https:// | ||
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