This version is outdated by a newer approved version.
This version (30 Sep 2013 11:55) is a draft.
Approvals: 0/1The Previously approved version (12 Apr 2013 15:31) is available.
This version (30 Sep 2013 11:55) is a draft.Approvals: 0/1The Previously approved version (12 Apr 2013 15:31) is available.
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Table of Contents
AD7780 Pmod Xilinx FPGA Reference Design
Introduction
The AD7780 is a complete low power front-end solution for bridge sensor products, including weigh scales, strain gages, and pressure sensors. It contains a precision, low power, 24-bit sigma-delta (Σ-Δ) ADC; an on-chip, low noise programmable gain amplifier (PGA); and an on-chip oscillator.
HW Platform(s):
Quick Start Guide
The bit file provided in the project *.zip file combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).
Required Hardware
Required Software
- Xilinx ISE 14.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
- A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard and ZedBoard or 9600 for the Digilent Nexys™3 Board.
Running Demo (SDK) Program
If you are not familiar with LX9 and/or Xilix tools, please visit
http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm for details.
If you are not familiar with Nexys™3 and/or Xilix tools, please visit
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3 for details.
If you are not familiar with ZedBoard and/or Xilix tools, please visit
http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx for details.
Avnet LX9 MicroBoard Setup
Extract the project from the archive file (AD7780_<board_name>.zip) to the location you desire.
To begin, connect the PmodAD3 to J5 connector of LX9 board (see image below). Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector.
Digilent Nexys™3 Spartan-6 FPGA Board
Extract the project from the archive file (AD7780_<board_name>.zip) to the location you desire.
To begin, connect the PmodAD3 to JA connector of Nexys™3 board (see image below). Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART).
Avnet ZedBoard
To begin, connect the PmodAD3 to JD connector of ZedBoard (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART).
FPGA Configuration for Nexys3 and LX-9 MicroBoard
Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal (set to appropiate baud rate) and then program the device using the bit file provided in the project *.zip archive, located in the “sw” folder (../ad7780/sw/AD7780.bit).
If programming was successful, the Main Menu will appear in your UART terminal, as seen in the pictures below. There are 6 options available for you. Use [v], [f], [g], [p], [r], [s], [m] in order to choose the desired one.
Display Vin allows printing the input voltage over the UART with the appropriate output rate (10 Hz or 16.7 Hz, depending on Filter settings). Pressing [m] will return to menu.
If the device is Powered Down the user will be prompted to Power Up the device prior to trying to display the input voltage.
Change Filter Option allows selecting between 10 Hz and 16.7 Hz Output Rate.
Change Gain Option allows selecting between a gain of 128 or a gain of 1.
Power Down / Power Up allows powering down the device or powering it back up.
Modify Voltage Reference allows changing the voltage reference that is used to calculate the value displayed over UART. The default value is 3300 mV. If using another reference voltage, please modify it here before printing values, in order to obtain correct results. If any value besides 1 to 9 is entered, an error message will be displayed. If a value higher than 5000 is entered, an error message will be displayed. If entering less than 4 characters, please press [Enter] in order to validate your input. If 4 characters are entered, the result is automatically validated.
Input errors are displayed in the following picture.
Display current settings allows printing the current settings for the device. Any pressed key will take you back to the menu.
FPGA Configuration for ZedBoard
Run the download.bat script from the “../bin” folder downloaded from the github (see the links in the download section of the wiki page). The script will automatically configure the ZYNQ SoC and download the *.elf file afterwards.
If the download script fails to run, modify the Xilinx Tools path in download.bat to match your Xilinx Installation path.
If programming was successful, you should be seeing messages appear on the terminal window as shown in the figure below. After programming the AD7780 device, the program will automatically read the value of the analog voltage input and print it via UART.
Using the reference design
Functional Description
The reference design is a custom communication interface, allowing control for the FILTER, GAIN, PDRST pins, reading data from the AD7780 and generating an interrupt when data has been received.
- UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard and ZedBoard or 9600 Baud Rate for the Digilent Nexys™3 Board.
- Reference voltage is 3300 mV default. If using another reference voltage, please check that the jumpers are properly set on the PmodAD3, and modify the reference voltage in the software application using UART (select option [r]).
- If using 3 external signals (AVDD, AIN and REF) then 2 jumpers on PmodAD3 must be off (JP1 and JP2).
- If using 2 external signals (AIN and REF) or (AIN and AVDD) then 1 jumper on PmodAD3 must be off (JP2 or JP1).
- Be aware that 0.5V ≤ Vref ≤ AVDD and 2.7V ≤ AVDD ≤ 5.25V.
- Be aware (especially when using gain = 128) that the common-mode voltage (AIN(+) + AIN(−)) / 2 must be ≥ 0.5V.
Downloads
Avnet LX-9 MicroBoard:
Digilent Nexys™3:
Avnet ZedBoard:
More information
- Example questions:
- An error occurred while fetching this feed: http://ez.analog.com/community/feeds/allcontent/atom?community=2061
resources/fpga/xilinx/pmod/ad7780.1380534917.txt.gz · Last modified: 30 Sep 2013 11:55 by Alexandru.Tofan