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resources:fpga:xilinx:pmod:ad7193 [22 Feb 2013 12:18] – archive and pictures Alexandru.Tofanresources:fpga:xilinx:pmod:ad7193 [09 Jan 2021 00:49] (current) – user interwiki links Robin Getz
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 **HW Platform(s):**  **HW Platform(s):** 
-   * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]] +   * [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]] 
    * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]    * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]
-   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-AD5|PmodAD5 (Digilent)]] \\ +   * [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx|Avnet ZedBoard]] \\
-**System:** Microblaze, AXI, UART \\+
  
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
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 ==== Required Hardware ==== ==== Required Hardware ====
-  * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]]    +  * [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]] 
-  * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]+  * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]   
 +  * [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx|Avnet ZedBoard]] 
   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-AD5|PmodAD5 (Digilent)]]   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-AD5|PmodAD5 (Digilent)]]
  
 ==== Required Software ==== ==== Required Software ====
-  * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). 
-  * A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard or 9600 for the Digilent Nexys™3 Board. +  * A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard and ZedBoard or 9600 for the Digilent Nexys™3 Board.
- +
  
 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
  
-<WRAP round tip 80%>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\ +<WRAP center round tip 80%>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\ 
-If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details. +If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details.\\ 
-</WRAP> +If you are not familiar with ZedBoard and/or Xilix tools, please visit\\ [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx]] for details.</WRAP>
-Extract the project from the archive file (AD7193_<board_name>.zip) to the location you desire. +
  
 ==== Avnet LX9 MicroBoard Setup ==== ==== Avnet LX9 MicroBoard Setup ====
 +
 +Extract the project from the archive file (AD7193_<board_name>.zip) to the location you desire. 
  
 To begin, connect the PmodAD5 to J5 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector. To begin, connect the PmodAD5 to J5 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector.
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 ==== Digilent Nexys™3 Spartan-6 FPGA Board ==== ==== Digilent Nexys™3 Spartan-6 FPGA Board ====
 +
 +Extract the project from the archive file (AD7193_<board_name>.zip) to the location you desire. 
  
 To begin, connect the PmodAD5 to JA connector of Nexys™3 board, pins JA1 to JA6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART). To begin, connect the PmodAD5 to JA connector of Nexys™3 board, pins JA1 to JA6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART).
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 {{:resources:fpga:xilinx:pmod:pmodad5_nexys3.jpg?200|PmodAD5 and Nexys™3}} {{:resources:fpga:xilinx:pmod:pmodad5_nexys3.jpg?200|PmodAD5 and Nexys™3}}
  
-==== FPGA Configuration ====+==== Avnet ZedBoard ==== 
 + 
 +To begin, connect the PmodAD5 to JA connector of ZedBoard (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART). 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodad5_zed.jpg?200|PmodAD5 and ZedBoard}} 
 + 
 +==== FPGA Configuration for Nexys3 and LX-9 MicroBoard ====
  
 Start IMPACT, and double click "Boundary Scan". Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal (set to appropiate baud rate) and then program the device using the bit file provided in the project *.zip archive, located in the "sw" folder (../ad7193/sw/AD7193.bit). Start IMPACT, and double click "Boundary Scan". Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal (set to appropiate baud rate) and then program the device using the bit file provided in the project *.zip archive, located in the "sw" folder (../ad7193/sw/AD7193.bit).
  
 {{:resources:fpga:xilinx:pmod:PmodAD5impact.jpg?200|Programming FPGA in IMPACT}} {{:resources:fpga:xilinx:pmod:PmodAD5impact.jpg?200|Programming FPGA in IMPACT}}
 +
 +==== FPGA Configuration for ZedBoard ====
 +
 +Run the **download.bat** script from the "../bin" folder downloaded from the github (see the links in the download section of the wiki page). 
 +The script will automatically configure the ZYNQ SoC and download the *.elf file afterwards.
 +
 +<WRAP center round tip 80%>
 +If the download script fails to run, modify the Xilinx Tools path in **download.bat** to match your Xilinx Installation path.
 +</WRAP>
  
 If programming was successful, you should be seeing messages appear on the terminal window as shown in the figures below. After programming the AD7193, the program will display the values of all internal registers. After that, it will go through 5 Demo Modes.  If programming was successful, you should be seeing messages appear on the terminal window as shown in the figures below. After programming the AD7193, the program will display the values of all internal registers. After that, it will go through 5 Demo Modes. 
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 ==== Functional Description ==== ==== Functional Description ====
  
-The reference design is a custom SPI Interface, containing CS, SCLK, MISO, MOSI, but also a GPIO to read the RDY status on the MISO line. The information is displayed on UART.+The reference design is a simple SPI Interface, containing CS, SCLK, MISO, MOSI, but also a GPIO to read the RDY status on the MISO line. The information is displayed on UART.
  
 The hardware SPI access allows sending and receiving data from the AD7193, programming its internal registers in order to decide which channels should be converted corresponding to AINCOM or its own differential pair, what GAIN, sampling frequency, etc. The hardware SPI access allows sending and receiving data from the AD7193, programming its internal registers in order to decide which channels should be converted corresponding to AINCOM or its own differential pair, what GAIN, sampling frequency, etc.
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 <WRAP round important 80%> <WRAP round important 80%>
   * Connecting the PmodAD5 to the boards using an extension cable provides ease of use.   * Connecting the PmodAD5 to the boards using an extension cable provides ease of use.
-  * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard or 9600 Baud Rate for the Digilent Nexys™3 Board.+  * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard and ZedBoard or 9600 Baud Rate for the Digilent Nexys™3 Board.
   * When using AVDD > DVDD (= 3.3V), JP1 on PmodAD5 must be removed. The range for AVDD is 3.0V ≤ AVDD ≤ 5.25V   * When using AVDD > DVDD (= 3.3V), JP1 on PmodAD5 must be removed. The range for AVDD is 3.0V ≤ AVDD ≤ 5.25V
   * If using Xilinx Software Development Kit integrated Console as a Hyperterminal clinet, please uncomment all the commented **getchar();** in main.c, because the Console sees [Enter] as 2 consecutive keypresses, so 2 getchar(); are required. If using Tera Term or other similar software, do not modify anything.    * If using Xilinx Software Development Kit integrated Console as a Hyperterminal clinet, please uncomment all the commented **getchar();** in main.c, because the Console sees [Enter] as 2 consecutive keypresses, so 2 getchar(); are required. If using Tera Term or other similar software, do not modify anything. 
 </WRAP> </WRAP>
  
 +<WRAP round important 80%>
 +When using the ZedBoard reference design in order to develop your own software, please make sure that the following options are set in "system_config.h":
 +
 +<code c>
 +// Select between PS7 or AXI Interface
 +#define USE_PS7 1
 +// SPI used in the design
 +#define USE_SPI 1
 +// I2C used in the design
 +#define USE_I2C 0
 +// Timer (+interrupts) used in the design
 +#define USE_TIMER 0
 +// External interrupts used in the design
 +#define USE_EXTERNAL     0
 +// GPIO used in the design
 +#define USE_GPIO         0
 +</code>
 +
 +</WRAP>
  
 ===== Downloads ===== ===== Downloads =====
 +
 <WRAP round download 80%> <WRAP round download 80%>
-{{:resources:fpga:xilinx:pmod:ad7193_lx9.zip|Reference design source code for Avnet LX9 MicroBoard.}} \\ +\\ 
-{{:resources:fpga:xilinx:pmod:ad7193_nexys3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}} \\ +**Avnet LX-9 MicroBoard: **\\ 
-</WRAP>+    * {{:resources:fpga:xilinx:pmod:ad7193_lx9.zip|Reference design source code for Avnet LX9 MicroBoard.}}\\
  
 +**Digilent Nexys™3:**\\
 +    * {{:resources:fpga:xilinx:pmod:ad7193_nexys3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}}\\
 +
 +**Avnet ZedBoard:**\\
 +    * [[https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_adv7511_zed|XPS Project]]\\
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodAD5|PmodAD5 Driver Files]]\\
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/Common/sw|ZYNQ SoC Peripherals Driver Files]] \\
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodAD5/bin|Programming Script]]\\
 +    
 +</WRAP>
  
 ===== More information ===== ===== More information =====
   * [[ez>community/fpga|ask questions about the FPGA reference design]]   * [[ez>community/fpga|ask questions about the FPGA reference design]]
   * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}   * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}
resources/fpga/xilinx/pmod/ad7193.1361531934.txt.gz · Last modified: 22 Feb 2013 12:18 by Alexandru.Tofan

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