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resources:fpga:xilinx:pmod:ad7193 [10 Dec 2012 15:51] – Download Wrapper Alexandru.Tofan | resources:fpga:xilinx:pmod:ad7193 [22 Feb 2013 12:18] – archive and pictures Alexandru.Tofan | ||
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==== Running Demo (SDK) Program ==== | ==== Running Demo (SDK) Program ==== | ||
- | <note tip>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http:// | + | <WRAP round tip 80%>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http:// |
If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http:// | If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http:// | ||
- | </note> | + | </WRAP> |
Extract the project from the archive file (AD7193_< | Extract the project from the archive file (AD7193_< | ||
==== Avnet LX9 MicroBoard Setup ==== | ==== Avnet LX9 MicroBoard Setup ==== | ||
- | To begin, connect the PmodAD5 to J5 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cables | + | To begin, connect the PmodAD5 to J5 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector. |
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==== Digilent Nexys™3 Spartan-6 FPGA Board ==== | ==== Digilent Nexys™3 Spartan-6 FPGA Board ==== | ||
- | To begin, connect the PmodAD5 to JA connector of Nexys™3 board, pins JA1 to JA6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board. | + | To begin, connect the PmodAD5 to JA connector of Nexys™3 board, pins JA1 to JA6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART). |
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If programming was successful, you should be seeing messages appear on the terminal window as shown in the figures below. After programming the AD7193, the program will display the values of all internal registers. After that, it will go through 5 Demo Modes. | If programming was successful, you should be seeing messages appear on the terminal window as shown in the figures below. After programming the AD7193, the program will display the values of all internal registers. After that, it will go through 5 Demo Modes. | ||
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**Read Voltage Values referenced to AINCOM, UNIPOLAR Mode.** | **Read Voltage Values referenced to AINCOM, UNIPOLAR Mode.** | ||
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**Read Voltage Values referenced to AINCOM, BIPOLAR Mode.** | **Read Voltage Values referenced to AINCOM, BIPOLAR Mode.** | ||
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**Read Differential Voltage Values, UNIPOLAR Mode.** | **Read Differential Voltage Values, UNIPOLAR Mode.** | ||
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**Read Differential Voltage Values, BIPOLAR Mode.** | **Read Differential Voltage Values, BIPOLAR Mode.** | ||
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**Read Die Temperature Value.** | **Read Die Temperature Value.** | ||
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===== Using the reference design ===== | ===== Using the reference design ===== | ||
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The hardware SPI access allows sending and receiving data from the AD7193, programming its internal registers in order to decide which channels should be converted corresponding to AINCOM or its own differential pair, what GAIN, sampling frequency, etc. | The hardware SPI access allows sending and receiving data from the AD7193, programming its internal registers in order to decide which channels should be converted corresponding to AINCOM or its own differential pair, what GAIN, sampling frequency, etc. | ||
- | <note important> | + | <WRAP round important |
* Connecting the PmodAD5 to the boards using an extension cable provides ease of use. | * Connecting the PmodAD5 to the boards using an extension cable provides ease of use. | ||
* UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard or 9600 Baud Rate for the Digilent Nexys™3 Board. | * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard or 9600 Baud Rate for the Digilent Nexys™3 Board. | ||
- | * Reference voltage | + | * When using AVDD > DVDD (= 3.3V), JP1 on PmodAD5 must be removed. The range for AVDD is 3.0V ≤ AVDD ≤ 5.25V |
* If using Xilinx Software Development Kit integrated Console as a Hyperterminal clinet, please uncomment all the commented **getchar(); | * If using Xilinx Software Development Kit integrated Console as a Hyperterminal clinet, please uncomment all the commented **getchar(); | ||
- | </note> | + | </WRAP> |
===== Downloads ===== | ===== Downloads ===== | ||
- | <WRAP round download | + | <WRAP round download |
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