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—resources:fpga:xilinx:pmod:ad7193 [09 Feb 2012 14:40] – added new archive Alexandru Tofan
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 +
 +
 +====== AD7193 Xilinx Pmod FPGA Reference Design ======
 + 
 +===== Introduction =====
 +
 +The [[adi>AD7193]] is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can interface directly to the ADC.
 +The device can be configured to have four differential inputs or eight pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled simultaneously, and the AD7193 sequentially converts on each enabled channel, simplifying communication with the part. The on-chip 4.92 MHz clock can be used as the clock source to the ADC or, alternatively, an external clock or crystal can be used. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz.
 +
 +**HW Platform(s):** [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]] [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-AD5|Pmod-AD5 (Digilent)]] \\
 +**System:** Microblaze, AXI, UART \\
 +
 +===== Quick Start Guide =====
 +
 +The bit file provided in the project *.zip file combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). 
 +
 +==== Required Hardware ====
 +  * LX9 microboard 
 +  * Pmod-AD5
 +
 +
 +==== Required Software ====
 +  * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
 +  * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
 +
 +
 +==== Running Demo (SDK) Program ====
 +
 +<note tip>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm]] for details.
 +</note>
 +Extract the project from the archive file (AD7193.zip) to the location you desire. 
 +
 +To begin, connect the Pmod-AD5 to J5 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board.
 +
 +{{:resources:fpga:xilinx:pmod:pmodad5.jpg?200|Pmod-AD5 and LX-9}}
 +
 +Start IMPACT, and double click "Boundary Scan". Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal (set to 57600 baud rate) and then program the device using the bit file provided in the project *.zip archive, located in the "sw" folder (../ad7193/sw/AD7193.bit).
 +
 +{{:resources:fpga:xilinx:pmod:PmodAD5impact.jpg?200|Programming FPGA in IMPACT}}
 +
 +If programming was successful, you should be seeing messages appear on the terminal window as shown in the figures below. After programming the AD7193, the program will display the values of all internal registers. After that, it will go through 3 Demo Modes: Read Voltage Values referenced to AINCOM, Read Differential Voltage Values and Read Die Temperature Value.
 +
 +{{:resources:fpga:xilinx:pmod:pmodad5demo1.jpg?200|UART messeges}}
 +{{:resources:fpga:xilinx:pmod:pmodad5demo2.jpg?200|UART messeges}}
 +{{:resources:fpga:xilinx:pmod:pmodad5demo3.jpg?200|UART messeges}}
 +{{:resources:fpga:xilinx:pmod:pmodad5demo4.jpg?200|UART messeges}}
 +
 +
 +===== Using the reference design =====
 +
 +==== Functional Description ====
 +
 +The reference design is a custom SPI Interface, containing CS, SCLK, MISO, MOSI, but also a GPIO to read the RDY status on the MISO line. The information is displayed on UART.
 +
 +The hardware SPI access allows sending and receiving data from the AD7193, programming its internal registers in order to decide which channels should be converted corresponding to AINCOM or its own differential pair, what GAIN, sampling frequency, etc.
 +
 +<note important>
 +  * Connecting the Pmod-AD5 to the LX-9 Board using an extension cable provides ease of use.
 +  * UART must be set to 57600 baudrate.
 +  * Reference voltage is 2.5V
 +</note>
 +
 +
 +===== Downloads =====
 +{{:resources:fpga:xilinx:pmod:ad7193new.zip|Reference design source code}} \\
 +
 +
 +===== More information =====
 +  * [[ez>community/fpga|ask questions about the FPGA reference design]]
  
resources/fpga/xilinx/pmod/ad7193.txt · Last modified: 09 Jan 2021 00:49 by Robin Getz

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