Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий
This version is outdated by a newer approved version.DiffThis version (30 Sep 2013 13:02) is a draft.
Approvals: 0/1The Previously approved version (12 Apr 2013 15:33) is available.Diff

This is an old revision of the document!

Table of Contents

AD7091R Pmod Xilinx FPGA Reference Design

Introduction

The AD7091R is a 12-bit, ultra low power, successive approximation ADC. The AD7091R operates from a single 2.7 V to 5.25 V power supply and is capable of achieving a sampling rate of 1 MSPS. The part contains a wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 7 MHz. The AD7091R also features an on-chip conversion clock, accurate reference and high-speed serial interface.

HW Platform(s):

Quick Start Guide

The bit file provided in the project *.zip file combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).

Required Hardware

Required Software

  • Xilinx ISE 14.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
  • A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard and ZedBoard or 9600 for the Digilent Nexys™3 Board.

Running Demo (SDK) Program

If you are not familiar with LX9 and/or Xilix tools, please visit
http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm for details.
If you are not familiar with Nexys™3 and/or Xilix tools, please visit
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3 for details.
If you are not familiar with ZedBoard and/or Xilix tools, please visit
http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx for details.

Avnet LX9 MicroBoard Setup

Extract the project from the archive file (AD7091R_<board_name>.zip) to the location you desire.

To begin, connect the PmodAD6 to J5 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board. Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector.

PmodAD6 and LX-9

Digilent Nexys™3 Spartan-6 FPGA Board

Extract the project from the archive file (AD7091R_<board_name>.zip) to the location you desire.

To begin, connect the PmodAD6 to JA connector of Nexys™3 board, pins JA1 to JA6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART).

PmodAD6 and Nexys™3

Avnet ZedBoard

To begin, connect the PmodAD6 to JD connector of ZedBoard (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART).

PmodAD6 and ZedBoard

FPGA Configuration for Nexys3 and LX-9 MicroBoard

Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal and then program the device using the bit file provided in the project *.zip archive, located in the “sw” folder (../ad7091R/sw/AD7091R.bit).

Programming FPGA in IMPACT

FPGA Configuration for ZedBoard

Run the download.bat script from the “../bin” folder downloaded from the github (see the links in the download section of the wiki page). The script will automatically configure the ZYNQ SoC and download the *.elf file afterwards.

If the download script fails to run, modify the Xilinx Tools path in download.bat to match your Xilinx Installation path.

If programming was successful, you should be seeing messages appear on the terminal window as shown in the figures below. After programming the AD7091R, you will be asked you to set the value of VREF.

UART messeges

If you use the default VREF(=2.5V) then just press [Enter] and the program will display the value of the input voltage. Pressing any key will perform another conversion and display the result.

UART messeges

Here you are some of the errors that can appear while trying to introduce a wrong value for VREF. If any value besides 1 to 9 is entered, an error message will be displayed. If a value higher than 5250 or lower than 2700 is entered, an error message will be displayed. If entering less than 4 characters, please press [Enter] in order to validate your input. If 4 characters are entered, the result is automatically validated.

UART messeges

Using the reference design

Functional Description

The reference design is a custom SPI Interface, containing CS, SCLK, MISO, and a CONVST signal.

The hardware SPI access allows receiving data from the AD7091R.

The software programs the device, and afterwards, using DMA, transfers 8192 samples and prints them on the UART.

  • Connecting the PmodAD6 to the boards using an extension cable provides ease of use.
  • UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard and ZedBoard or 9600 Baud Rate for the Digilent Nexys™3 Board.
  • When using AVDD > DVDD (= 3.3V), JP1 on PmodAD6 must be removed and the external AVDD signal must be connected to J2 Pin 1. The range for AVDD is 2.7V ≤ AVDD ≤ 5.25V.
  • When using external VREF, connect the VREF signal to J2 Pin 3. The range for external VREF is 2.7V ≤ VREF ≤ AVDD.

Downloads

</WRAP>


Avnet LX-9 MicroBoard:

Digilent Nexys™3:

Avnet ZedBoard:

More information

resources/fpga/xilinx/pmod/ad7091r.1380538956.txt.gz · Last modified: 30 Sep 2013 13:02 by Alexandru.Tofan

Page Tools