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resources:fpga:xilinx:pmod:ad7091r [12 Apr 2013 15:33] – [Downloads] Lucian Sinresources:fpga:xilinx:pmod:ad7091r [01 Oct 2013 09:23] – [FPGA Configuration for ZedBoard] Alexandru.Tofan
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    * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]]     * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]] 
    * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]    * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]
-   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-AD6|PmodAD6 (Digilent)]] \\ +   * [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx|Avnet ZedBoard]] \\
-**System:** Microblaze, AXI, UART \\+
  
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
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 ==== Required Hardware ==== ==== Required Hardware ====
-  * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]]    +  * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]] 
-  * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]+  * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]   
 +  * [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx|Avnet ZedBoard]]  
   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-AD6|PmodAD6 (Digilent)]]   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-AD6|PmodAD6 (Digilent)]]
  
 ==== Required Software ==== ==== Required Software ====
-  * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). 
-  * A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard or 9600 for the Digilent Nexys™3 Board.+  * A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard and ZedBoard or 9600 for the Digilent Nexys™3 Board.
  
 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
  
-<WRAP round tip 80%>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\ +<WRAP center round tip 80%>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\ 
-If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details. +If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details.\\ 
-</WRAP> +If you are not familiar with ZedBoard and/or Xilix tools, please visit\\ [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx]] for details.</WRAP>
-Extract the project from the archive file (AD7091R_<board_name>.zip) to the location you desire. +
  
 ==== Avnet LX9 MicroBoard Setup ==== ==== Avnet LX9 MicroBoard Setup ====
 +
 +Extract the project from the archive file (AD7091R_<board_name>.zip) to the location you desire. 
  
 To begin, connect the PmodAD6 to J5 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board. Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector. To begin, connect the PmodAD6 to J5 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board. Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector.
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 ==== Digilent Nexys™3 Spartan-6 FPGA Board ==== ==== Digilent Nexys™3 Spartan-6 FPGA Board ====
 +
 +Extract the project from the archive file (AD7091R_<board_name>.zip) to the location you desire. 
  
 To begin, connect the PmodAD6 to JA connector of Nexys™3 board, pins JA1 to JA6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART). To begin, connect the PmodAD6 to JA connector of Nexys™3 board, pins JA1 to JA6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART).
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 {{:resources:fpga:xilinx:pmod:pmodad6_nexys3.jpg?200|PmodAD6 and Nexys™3}} {{:resources:fpga:xilinx:pmod:pmodad6_nexys3.jpg?200|PmodAD6 and Nexys™3}}
  
-==== FPGA Configuration ====+==== Avnet ZedBoard ==== 
 + 
 +To begin, connect the PmodAD6 to JD connector of ZedBoard (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART). 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodad6_zed.jpg?200|PmodAD6 and ZedBoard}} 
 + 
 +==== FPGA Configuration for Nexys3 and LX-9 MicroBoard ====
  
 Start IMPACT, and double click "Boundary Scan". Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal and then program the device using the bit file provided in the project *.zip archive, located in the "sw" folder (../ad7091R/sw/AD7091R.bit). Start IMPACT, and double click "Boundary Scan". Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal and then program the device using the bit file provided in the project *.zip archive, located in the "sw" folder (../ad7091R/sw/AD7091R.bit).
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 {{:resources:fpga:xilinx:pmod:pmodad6_menu2.jpg?600|UART messeges}} {{:resources:fpga:xilinx:pmod:pmodad6_menu2.jpg?600|UART messeges}}
  
-Here you are some of the errors that can appear while trying to introduce a wrong value for VREF.+Here are some of the errors that can appear while trying to introduce a wrong value for VREF.
 If any value besides 1 to 9 is entered, an error message will be displayed. If a value higher than 5250 or lower than 2700 is entered, an error message will be displayed. If entering less than 4 characters, please press [Enter] in order to validate your input. If 4 characters are entered, the result is automatically validated. If any value besides 1 to 9 is entered, an error message will be displayed. If a value higher than 5250 or lower than 2700 is entered, an error message will be displayed. If entering less than 4 characters, please press [Enter] in order to validate your input. If 4 characters are entered, the result is automatically validated.
  
 {{:resources:fpga:xilinx:pmod:pmodad6_menu3.jpg?600|UART messeges}} {{:resources:fpga:xilinx:pmod:pmodad6_menu3.jpg?600|UART messeges}}
 +
 +
 +==== FPGA Configuration for ZedBoard ====
 +
 +Run the **download.bat** script from the "../bin" folder downloaded from the github (see the links in the download section of the wiki page). 
 +The script will automatically configure the ZYNQ SoC and download the *.elf file afterwards.
 +
 +<WRAP center round tip 80%>
 +If the download script fails to run, modify the Xilinx Tools path in **download.bat** to match your Xilinx Installation path.
 +</WRAP>
 +
 +If programming was successful, you should be seeing messages appear on the terminal window. The software is programmed with VRef = 2.5 V. If you wish to change Vref, you must modify its value in main.c.
  
 ===== Using the reference design ===== ===== Using the reference design =====
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 ==== Functional Description ==== ==== Functional Description ====
  
-The reference design is a custom SPI Interface, containing CS, SCLK, MISO, and a CONVST signal.+=== Avnet LX-9 MicroBoard and Digilent Nexys3 ===
  
-The hardware SPI access allows receiving data from the AD7091R.+The reference design is a custom SPI Interface, containing CS, SCLK, MISO, and a CONVST signal. The hardware SPI access allows receiving data from the AD7091R. The software programs the device, and afterwards, prints the input voltage value via UART. 
 + 
 +=== Avnet ZedBoard === 
 + 
 +The reference design is a custom SPI Interface, containing CS, SCLK, MISO, and a CONVST signal. The hardware SPI access allows receiving data from the AD7091R. The software programs the device, and afterwards, using DMA, transfers 8192 samples and prints the input voltage value via UART.
  
 <WRAP round important 80%> <WRAP round important 80%>
   * Connecting the PmodAD6 to the boards using an extension cable provides ease of use.   * Connecting the PmodAD6 to the boards using an extension cable provides ease of use.
-  * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard or 9600 Baud Rate for the Digilent Nexys™3 Board.+  * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard and ZedBoard or 9600 Baud Rate for the Digilent Nexys™3 Board.
   * When using AVDD > DVDD (= 3.3V), JP1 on PmodAD6 must be removed and the external AVDD signal must be connected to J2 Pin 1. The range for AVDD is 2.7V ≤ AVDD ≤ 5.25V.   * When using AVDD > DVDD (= 3.3V), JP1 on PmodAD6 must be removed and the external AVDD signal must be connected to J2 Pin 1. The range for AVDD is 2.7V ≤ AVDD ≤ 5.25V.
-When using external VREF, connect the VREF signal to J2 Pin 3. The range for external VREF is 2.7V ≤ VREF ≤ AVDD.+  * When using external VREF, connect the VREF signal to J2 Pin 3. The range for external VREF is 2.7V ≤ VREF ≤ AVDD.
  
 </WRAP> </WRAP>
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 ===== Downloads ===== ===== Downloads =====
 +
 <WRAP round download 80%> <WRAP round download 80%>
 \\ \\
-{{:resources:fpga:xilinx:pmod:ad7091r_lx9.zip|Reference design source code for Avnet LX9 MicroBoard.}} \\ +**Avnet LX-9 MicroBoard: **\\ 
-{{:resources:fpga:xilinx:pmod:ad7091r_nexys3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}} \\ +    * {{:resources:fpga:xilinx:pmod:ad7091r_lx9.zip|Reference design source code for Avnet LX9 MicroBoard.}}\\
-</WRAP>+
  
 +**Digilent Nexys™3:**\\
 +    * {{:resources:fpga:xilinx:pmod:ad7091r_nexys3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}} \\
 +
 +**Avnet ZedBoard:**\\
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodAD6/cf_ad7091r_zed|XPS Project]]\\
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodAD6/cf_lib/edk/pcores/axi_ad7091r_v1_00_a|AD7091R IPCore]] \\
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/Common/cf_lib|Required Project Libraries]]\\
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodAD6|PmodAD6 Driver Files]]\\
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodAD6/bin|Programming Script]]\\
 +    
 +</WRAP>
  
 ===== More information ===== ===== More information =====
   * [[ez>community/fpga|ask questions about the FPGA reference design]]   * [[ez>community/fpga|ask questions about the FPGA reference design]]
   * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}   * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}
resources/fpga/xilinx/pmod/ad7091r.txt · Last modified: 09 Jan 2021 00:49 by Robin Getz

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