This version (16 Jul 2015 13:14) was approved by LucianS.The Previously approved version (16 Jul 2015 09:49) is available.Diff

ADV7511 Xilinx Evaluation Boards Reference Design


The ADV7511 is a 225 MHz High-Definition Multimedia Interface (HDMI®) transmitter. It is part of the Artix-7 AC701, Kintex-7 KC705, Virtex-7 VC707, Zynq ZC702, Zynq ZC706 and the Zynq ZED evaluation boards. This reference design provides the video and audio interface between the FPGA and ADV7511 on board. The video uses a 16bit 422 YCbCr interface (except VC707 which uses 36bit 444 RGB interface) and the audio uses a single bit SPDIF interface.

Supported Carriers

Required Hardware

  • AC701/KC705/VC707/ZC702/ZC706/Zed board.
  • HDMI Monitor.

Required Software

  • We're upgrade the Xilinx tools on every release. The supported version number can be found in our git repository .
  • A UART terminal (Tera Term/Hyperterminal) - baud rate 115200

Running Demo (SDK) Program

To begin, connect an HDMI cable between the board HDMI out and the HDMI monitor. After the hardware setup, turn the power on to the board.

Run the evaluate.bat script. This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR.

Note: If your Xilinx installation path is different than the one specified in the evaluate.bat, please modify the script accordingly.

If programming was successful, you should be seeing messages appear on the terminal as shown in figure below.


The reference design contains an example of how to:

  • Initialize the ADV7511 High-Definition Multimedia Interface (HDMI®) transmitter.
  • Check current AVR operating mode and depending on this result set the AV mute state.
  • Display an image and play a sound.

Using the reference design

Functional description

Block Diagram

The reference design consists of two independent pcore modules.

The video part consists of a Xilinx VDMA interface and the ADV7511 video interface. The ADV7511 interface consists of a 16bit YCbCr 422 with separate synchorinzation signals. The VDMA streams frame data to this core. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable.

The reference design defaults to the 1080p video mode. Users may change the video settings by programming the following registers. The core requires a corresponding pixel clock to generate the video. This clock must be generated externally.

HSYNC count: is the total horizontal pixel clocks of the video, for 1080p this is 2200.
HSYNC width: is the pulse width in pixel clocks, for 1080p this is 44.
HSYNC DE Minimum: is the number of pixel clocks for the start of active video and is the sum of horizontal sync width and back porch, for 1080p this is 192 (44 + 148).
HSYNC DE Maximum: is the number of pixel clocks for the end of active video and is the sum of horizontal sync width, back porch and the active video count, for 1080p this is 2112 (44 + 148 + 1920).

VSYNC count: is the total vertical pixel clocks of the video, for 1080p this is 1125.
VSYNC width: is the pulse width in pixel clocks, for 1080p this is 5.
VSYNC DE Minimum: is the number of pixel clocks for the start of active video and is the sum of vertical sync width and back porch, for 1080p this is 41 (5 + 36).
VSYNC DE Maximum: is the number of pixel clocks for the end of active video and is the sum of vertical sync width, back porch and the active video count, for 1080p this is 1121 (5 + 36 + 1080).

Note that the pixel frequency for 1080p is 148.5MHz.

The reference design reads 24bits of RGB data from DDR and performs color space conversion (RGB to YCbCr) and down sampling (444 to 422). If bypassed, the lower 16bits of DDR data is passed to the HDMI interface as it is.

A color pattern register provides a quick check of any RGB values on the monitor. If enabled, the register data is used as the pixel data for the entire frame.

The audio part consists of a Xilinx DMA interface and the ADV7511 spdif audio interface. The audio clock is derived from the bus clock. A programmable register (see below) controls the division factor. The audio data is read from the DDR as two 16bit words for the left and right channels. It is then transmitted on the SPDIF frame. The sample frequency and format may be controlled using the registers below. The reference design defaults to 48KHz.


Please refer to the regmap.txt file inside the pcores.

Audio Registers (axi_spdif_tx)

QW Address1 Bits Default Name Description
0x00 23:20 0 mode Sample format 0 to 8 (0-16bit, 8-24bit).
15:8 0 ratio Clock divider for the transmit frequency = bus_clock/(1+ratio).
1 0 txdata Transmit data buffer enable (0x1) or disable (0x0).
0 0 txenable Transmitter enable (0x1) or disable (0x0).
0x01 7:6 0 frequency Sample frequency 0(44.1KHz), 1(48KHz), 2(32KHz) or 3(sample rate converter) (RO).
3 0 gstat Generation status original/commercially pre-recorded data (0x1) or none (0x0) (RO).
2 0 pre-emphasis Pre-emphasis 50/15s (0x1) or none (0x0) (RO).
1 0 copy Copy permitted (0x1) or inhibited (0x0) (RO).
0 0 audio Data format is non-audio (0x1) or audio (0x0) (RO).
1. For AXI-Lite byte addresses, multiply by 4.

Using the Software Reference Design

The Software Reference Design uses the ADV7511 Transmitter Library which is a collection of APIs that provide a consistent interface to ADV7511. The library is a software layer that sits between the application and the TX hardware and it is intended to serve two purposes:

  • Provide the application with a set of APIs that can be used to configure HDMI TX hardware without the need for low-level register access. This makes the application portable across different revisions of the hardware and even across different hardware modules.
  • Provide basic services to aid the application in controlling the TX module, such as interrupt service routine, HDCP high-level control and status information.

The documentation for the library's API can be accessed here: <fs 120%>ADV7511 Transmitter API Documentation</fs>

The project contains 2 components: the Reference Design files and the ADV7511 Transmitter Library. All the components have to be downloaded from the links provided in the Downloads section.

Software Setup for Vivado

Example for a ZC702 board:

  • After building the project in Vivado for the used FPGA board, a SDK_Export folder will be created in ../adv7511_board.sdk/SDK
  • Open the Xilinx SDK for Vivado. When the SDK starts it asks to provide a folder where to store the workspace. Any folder can be provided.
  • Go to File→New→Application project

 New Application Project

  • Use a new hardware platform, so choose New in Target Hardware section

 New Platform

  • At the Target Hardware Specification section browse the location of the hardware description file. This file's extension should be .xml or .hdf, and is located in the directory of the hdl design. Note: If the file does not exist, probably you forgot to make an Export hardware (in Vivado FileExportExport Hardware…)

 New Hardware Project

  • Then give a name to the project and click Next

 Project Name

  • In the next window choose Empty Application and click Finish

 Available Templates

  • Now the project without source code looks like this

 Empty Project

  • Then the no-OS software for the used FPGA board must be added from Github. Also the library must be added (ZC library for a Zynq based platform(except ZED), ZED library for a ZED platform or Microblaze library for AC701,KC705,VC707).

 Project without directory and library path

  • Afterwards click right on project name and go to Properties

 Project properties

  • In the window that appears, go to Settings→Directories and include the path of the inc directory for both Debug and Release configurations.

 Include directory path

  • In the same window, go to Settings→Libraries and add the path of the lib folder and the name of the library used. For a Zynq based platform the name is HDMI_ZynqLib (libHDMI_ZynqLib.a on Github) and for a Microblaze the name is HDMI_MicroblazeLib (libHDMI_MicroblazeLib.a on Github)

 Include library path

  • The Project Explorer window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the Console window will display the result of the build. If the build is not done automatically select the Project→Build Automatically menu option.

 Project Explorer

  • At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. You can program the FPGA by going to Xilinx Tools.

 Program FPGA

  • Then choose this bitstream and press Program.

 Program FPGA with bitstream

  • This window will appear next.

 Program FPGA progress

  • Afterwards a Run Configuration must be created and then press Run.

 Run Configuration

  • The no-OS drivers source code does the following actions:
    • Initializes the HDMI core;
    • Initializes the ADV7511 part;
    • Transmits to a HDMI capable monitor an image whoose resolution can be changed by typing in the terminal a number from 0 to 6;
    • Transmits to a HDMI capable monitor a sound.
  • This is what is transmitted through UART:


  • The output of the example program can be viewed in the SDK console by enabling the Connect STDIO Console option and setting the baud rate of the UART port to 115200.

 STDIO configuration

As an alternative an UART terminal can be used to capture the output of the example program. The number of used UART port depends on the computer's configuration. The following settings must be used in the UART terminal:

  • Baud Rate: 115200bps
  • Data: 8 bit
  • Parity: None
  • Stop bits: 1 bit
  • Flow Control: none


The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices Github.

Evaluation Scripts:

HDL Reference Designs:

no-OS Software:

More information

resources/fpga/xilinx/kc705/adv7511.txt · Last modified: 16 Jul 2015 13:13 by LucianS