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--- resources:fpga:xilinx:kc705:adv7511 [18 Nov 2019 15:56] – Stanca-Florina Pop
+++ resources:fpga:xilinx:kc705:adv7511 [18 Nov 2019 16:03] – Stanca-Florina Pop
@@ Line 54: / Line 54: @@
 {{resources:fpga:xilinx:fmc:fmc-imageon:adv7511_proc_1.svg?600|HDL Block Diagram}}
-The reference design consists of two independent IP modules.
+The reference design consists of two independent pcore modules.
 The video part consists of an AXI DMAC interface and the ADV7511 video interface. The ADV7511 interface consists of a 16bit YCbCr 422 with separate synchroinzation signals. The DMA streams frame data to this core. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable.

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