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- 02-064617-01-d_pub_25july2022.pdf
- 25 Jul 2022 20:50
- 1.4 MB
- 05-048950-b_bom.zip
- 12 Dec 2019 16:03
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- 2020-05-15_ad9213_evalbrd_revc_bom_w_dut.xlsx
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- ad974xacp-pcbz_ug-1650.pdf
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- 17 Mar 2021 01:27
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- 29 Aug 2022 19:18
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- 23 Nov 2021 17:29
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- 22 Jan 2022 00:42
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- 22 Jan 2022 00:42
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- ad9213_layout_files.zip
- 07 Sep 2022 23:47
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- ad9213_onboard_clocking_bom.xlsx
- 07 Sep 2022 23:50
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- 30 Aug 2019 15:53
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- ad9249_fmc_brd_designfiles.zip
- 06 Apr 2021 19:34
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- 28 Apr 2021 12:09
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- adalm2000_pinout.pdf
- 20 Jun 2017 16:53
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- adiplutoworkshop_grcon2019.pdf
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- board.ad9213.0.1.7.zip
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![[root]](/resources/fpga/xilinx/interposer/common_sdp?ns=&tab_files=files&do=media&tab_details=view&image=resources%3Afpga%3Adocs%3Ahdl%3Afmcomms2_fir_rx_active_fft.png){kind=link}
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- 923
- References for:
- Integrate FIR filters into the FMCOMMS2 HDL design
resources/fpga/xilinx/interposer/common_sdp.txt · Last modified: 28 Sep 2012 10:32 by Adrian Costina