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CN0235 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design

Supported Devices

Reference Circuits


This document presents the steps to setup an environment for using the EVAL-CN0235-SDPZ evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the Micrium µC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-CN0235-SDPZ Evaluation Board with the Xilinx KC705 board.


For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:

  • 1. A controller board like the SDP-B ( EVAL-SDP-CS1Z)
  • 2. The component SDP compatible product evaluation board
  • 3. Corresponding PC software ( shipped with the product evaluation board)

The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.

Note: it is expected that the analog performance on the two platforms may differ.

28 Sep 2012 10:32 · AdrianC

Below is presented a picture of SDP-B Controller Board with the EVAL-CN0235-SDPZ Evaluation Board.


The CN0235 board is a fully isolated lithium ion battery monitoring and protection system. Lithium ion (Li-Ion) battery stacks contain a large number of individual cells that must be monitored correctly in order to enhance the battery efficiency, prolong the battery life, and ensure safety.

The AD7280A contains all the functions required for general-purpose monitoring of stacked lithium ion batteries as used in hybrid electric vehicles, battery backup applications, and power tools. The part has multiplexed cell voltage and auxiliary ADC measurement channels for up to six cells of battery management. An internal ±3 ppm/°C reference is provided that allows a cell voltage accuracy of ±1.6 mV. The ADC resolution is 12 bits and allows conversion of up to 48 cells within 7 us.

The AD8280 is a hardware-only safety monitor for lithium ion battery stacks. The part has inputs to monitor six battery cells and two temperature sensors (either NTC or PTC thermistors). The part is designed to be daisy-chained with other AD8280 devices to monitor a stack of significantly more than six cells without the need for numerous isolators. Its output can be configured for an independent or shared alarm state.

More information

Getting Started

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

Required Hardware

Required Software

  • Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
  • uC-Probe run-time monitoring tool


The following table presents a short description the reference design archive contents.

Folder Description
Bit Contains the KC705 configuration file that can be used to program the system for quick evaluation.
Microblaze Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA.
Software Contains the source files of the software project that will be run by the Microblaze processor.
uCProbeInterface Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory.

Run the Demonstration Project

Hardware Setup

Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.

  • Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
  • Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  • Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Kintex 7 device (see screenshot below).

  • Program the KC705 FPGA using the “Bit/download.bit” file provided in the reference design archive.
  • Power the ADI evaluation board.

At this point everything is set up and it is possible to start the evaluation of the ADI hardware through the controls in the uC-Probe application provided in the reference design.

Configure uC-Probe

Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.

Select uC-Probe options.

  • Click on the uC-Probe icon on the top left portion of the screen.
  • Click on the Options button to open the dialog box.

Set target board communication protocol as RS-232

  • Click on the Communication tab icon on the top left portion of the dialog box
  • Select the RS-232 option.

Setup RS-232 communication settings

  • Select the RS-232 option from the Communication tab.
  • Select the COM port to which the KC705 board is connected.
  • Set the Baud Rate to 115200 bps.

  • Press Apply and OK to exit the options menu.

Load and Run the Demonstration Project

  • Click the Open option from the uC-Probe menu and select the .wsp file from the ucProbeInterface folder provided within the reference design files.
  • Before opening the interface uC-Probe will ask for a symbols file that must be associated with the interface. Select the file ucProbeInterface/ADIEvalBoard.elf to be loaded as a symbol file.
  • Run the demonstration project by pressing the Play button.

  • In some cases it is possible that the uC-Probe interface will not respond to the commands the first time it is ran. In this situation just stop the interface by pressing the Stop button and run it again by pressing the Play button.
  • After starting the uC-Probe interface wait until the status of the connection with the board displayed on the bottom of the screen is set to Connected. It is possible to use the interface only after the status is changed to Connected and the data transfer speed displayed next to the connection status is different than 0.
16 Feb 2012 09:23 · acozma

Demonstration Project User Interface

The following figures present the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-CN0235-SDPZ evaluation board.

Section A is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. If the ON/OFF switch is set to ON and the Activity* LED is BLACK it means that there is a communication problem with the board. See the Troubleshooting section for indications on how to fix the communication problems.

Section B is used to acquire data from the two AD7280As from the circuit. When pressing the Convert All button a conversion and a read will be initiated. The data read will be then converted to voltages before being displayed on the interface.

Section C is used to perform self test for both AD7280As. The data from the Self test registers will be displayed as voltage.

Section D displays the status of the ALERT pin on the master AD7280A. By default, the alert is not activated, so a configuration of the Alert register and Overvoltage/Undervoltage register is needed before the alerts can be displayed.

Section E allows to toggle the PD pin. If the pin is low, the AD7280As will be powered down.

Section F is used to activate/deactivate the AD8280s, used as secondary safety monitor. By hardware, the Overvoltage is set to 4 V and Undervoltage is set to 2 V. In case one of the cells goes beyound these voltages, the LEDs will indicate that. By pressing the Self Test button, the self test feature can be evaluated.

Section G is used to perform readings of any of the registers on the 2 AD7280a devices. Before pressing the Read button, the device on which the read is to be performed must be selected and also the register number. When reading from the Slave device, the LED will be ON. As a response the device address, register address and register data will be displayed, all in decimal.

Section A is used to select the address of the devive on which the register should be configured. The LED is on when the Slave device is selected.

Section B is used to configure the Control High Byte register. The first slider from left to right will select the conversion inputs. The second slider will select the conversion results that should be read. The third button configures the conversion start format. The forth slider enables/disables conversion averaging. The fith button selects the power-down format.

Section C is used to configure the Control Low Byte register. The first button from left to right will perform a software reset. The second slider will set the acquisition time. The third button will enable/disable the thermistor termination resistor. The fourth button can be used to lock the part to the new device address. The fith button allows incrementing the device address. THe last button will enable/disable the daisy chain register readback.

Section D is used to configure the Alert register and the Undevoltage/Overvoltage registers. By default no alert signals are generated or passed. When moving the sliders for the undervoltage/overvoltage registers, the voltage corresponding to that value will be displayed.

Section E is used to configure the Cell Balance register. By default the register is set to 0.

Section F is used to configure the Cell Balance timers registers. By default the timers are set to 0.

Section G is used to configure the Power Down timer. By default the timer is set to 0.


In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues:

  • Check that the evaluation board is powered as instructed in the board's user guide.
  • In uC-Probe refresh the symbols file by right-clicking on the System Browser window and selecting Refresh Symbols.
  • If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.

More information

28 May 2012 15:18
resources/fpga/xilinx/interposer/cn0235.1353083464.txt.gz · Last modified: 16 Nov 2012 17:31 by larsc