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resources:fpga:xilinx:interposer:cn0235 [16 Nov 2012 17:31]
larsc [Evaluation Boards]
resources:fpga:xilinx:interposer:cn0235 [20 Jan 2014 15:01]
LucianS changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>​CN0235|EVAL-CN0235-SDPZ]]** evaluation board together with the Xilinx KC705 FPGA boardthe Xilinx Embedded Development Kit (EDK) and the [[http://​micrium.com/​page/​products/​tools/​probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-CN0235-SDPZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>​CN0235|EVAL-CN0235-SDPZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-CN0235-SDPZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :​resources:​fpga:​xilinx:​interposer:​cn0235.jpg?​400 }} {{ :​resources:​fpga:​xilinx:​interposer:​cn0235.jpg?​400 }}
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   * [[adi>/​static/​imported-files/​circuit_notes/​CN0235.pdf|EVAL-CN0235-SDPZ evaluation board user guide]]   * [[adi>/​static/​imported-files/​circuit_notes/​CN0235.pdf|EVAL-CN0235-SDPZ evaluation board user guide]]
   * [[http://​www.xilinx.com/​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://​www.xilinx.com/​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://​micrium.com/​page/​products/​tools/​probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack)+  * Xilinx ISE 14.6
-  * [[http://micrium.com/​page/​products/​tools/​probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal),​ baud rate 115200. 
 +  * The EVAL-CN0235 reference project for Xilinx KC705 FPGA. 
  
 ===== Downloads ===== ===== Downloads =====
- +<WRAP round download 80%> 
-  * {{:resources:​fpga:xilinx:​interposer:​cn0235_evalboard.zip|Reference Design Files}} +\\ 
- +  * **AD7280A Driver:** https://github.com/​analogdevicesinc/​no-OS/​tree/​master/​device_drivers/​AD7280A 
-The following table presents a short description the reference design archive contents. +  * **CN0235 Commands:** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/​device_commands/​CN0235 
- +  ​* **Xilinx Boards Common Drivers:** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/​platform_drivers/​Xilinx/​SDP_Common 
-**Folder** **Description** +  * **EDK KC705 Reference ​project:** https://​github.com/​analogdevicesinc/​fpgahdl_xilinx/​tree/​master/​cf_sdp_kc705 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation| +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +</​WRAP>​
-| Software | Contains the source files of the software ​project ​that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. | +
 ====== Run the Demonstration Project ====== ====== Run the Demonstration Project ======
  
-{{page>​ucprobe_common}} +===== Hardware setup =====
- +
-===== Demonstration Project User Interface ​===== +
- +
-The following figures present the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-CN0235-SDPZ** evaluation board. +
- +
-{{ :​resources:​fpga:​altera:​bemicro:​cn0235_interface_monitor.png?​800 }} +
- +
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the //ON/OFF// switch. The //​Activity//​ LED turns green when the communication is active. If the //ON/OFF// switch is set to //ON// and the //​Activity//​* LED is **//​BLACK//​** it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. +
- +
-**Section B** is used to acquire data from the two AD7280As from the circuit. When pressing the //Convert All// button a conversion and a read will be initiated. The data read will be then converted to voltages before being displayed on the interface. +
- +
-**Section C** is used to perform self test for both AD7280As. The data from the //Self test// registers will be displayed as voltage. +
- +
-**Section D** displays the status of the //ALERT// pin on the master AD7280A. By default, the alert is not activated, so a configuration of the //Alert// register and //​Overvoltage/​Undervoltage//​ register is needed before the alerts can be displayed. +
- +
-**Section E** allows to toggle the //PD// pin. If the pin is low, the AD7280As will be powered down. +
- +
-**Section F** is used to activate/​deactivate the AD8280s, used as secondary safety monitor. By hardware, the //​Overvoltage//​ is set to 4 V and //​Undervoltage//​ is set to 2 V. In case one of the cells goes beyound these voltages, the LEDs will indicate that. By pressing the //Self Test// button, the self test feature can be evaluated. +
- +
-**Section G** is used to perform readings of any of the registers on the 2 AD7280a devices. Before pressing the //Read// button, the device on which the read is to be performed must be selected and also the register number. When reading from the Slave device, the LED will be ON. As a response the device address, register address and register data will be displayed, all in decimal. +
- +
-{{ :​resources:​fpga:​altera:​bemicro:​cn0235_interface_control.png?​800 }} +
- +
-**Section A** is used to select the address of the devive on which the register should be configured. The LED is on when the Slave device is selected. +
- +
-**Section B** is used to configure the //Control High Byte// register. The first slider from left to right will select the conversion inputs. The second slider will select the conversion results that should be read. The third button configures the conversion start format. The forth slider enables/​disables conversion averaging. The fith button selects the power-down format.+
  
-**Section C** is used to configure ​the //Control Low Byte// register. The first button from left to right will perform a software resetThe second slider will set the acquisition timeThe third button will enable/​disable the thermistor termination resistor. The fourth button can be used to lock the part to the new device addressThe fith button allows incrementing the device address. THe last button will enable/disable the daisy chain register readback.+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3VFor more details on how to change ​the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-**Section D** is used to configure ​the //Alert// register and the //​Undevoltage/​Overvoltage//​ registers. By default no alert signals are generated or passedWhen moving ​the sliders for the undervoltage/​overvoltage registers, ​the voltage corresponding to that value will be displayed.+  ​Use the FMC-SDP interposer ​to connect ​the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect ​the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-**Section E** is used to configure ​the //Cell Balance// ​register. ​By default ​the register ​is set to 0.+===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-CN0235 reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +**help?** | Displays all available commands. | 
 +| **adcCode?​** | Displays ​the ADC code of one channel from selected device. Accepted values: \\  device:\\ 0 - master\\ 1 - slave\\ register address:\\ 0 - Cell Voltage 1\\ 1 - Cell Voltage 2\\ 2 - Cell Voltage 3\\ 3 - Cell Voltage 4\\ 4 - Cell Voltage 5\\ 5 - Cell Voltage 6\\ 6 - AUX ADC 1\\ 7 - AUX ADC 2\\ 8 - AUX ADC 3\\ 9 - AUX ADC 4\\ 10 - AUX ADC 5\\ 11 - AUX ADC 6 | 
 +| **voltage?​** | Displays the input voltage of one channel from selected device. Accepted values: \\  device:\\ 0 - master\\ 1 - slave\\ register address:\\ 0 - Cell Voltage 1\\ 1 - Cell Voltage 2\\ 2 - Cell Voltage 3\\ 3 - Cell Voltage 4\\ 4 - Cell Voltage 5\\ 5 - Cell Voltage 6\\ 6 - AUX ADC 1\\ 7 - AUX ADC 2\\ 8 - AUX ADC 3\\ 9 - AUX ADC 4\\ 10 - AUX ADC 5\\ 11 - AUX ADC 6 | 
 +| **register?​** | Displays the content of one register ​from selected deviceAccepted values:\\ device:\\ 0 - master\\ 1 - slave\\ register address:\\ 13 - Control high byte\\ 14 - Control low byte\\ 15 - Cell Overvoltage\\ 16 - Cell Undervoltage\\ ... (see AD7280A_Datasheet p.28)\\ 29 - CNVST Control | 
 +| **register=** | Sets the content of one register ​from selected device. ​ Accepted values:\\ device:\\ 0 - master\\ 1 - slave\\ register address:\\ 13 - Control high byte\\ 14 - Control low byte\\ 15 - Cell Overvoltage\\ 16 - Cell Undervoltage\\ ... (see AD7280A_Datasheet p.28)\\ 29 - CNVST Control\\ register value:\\ 0 .. 255 - value to be written inside the register. | 
 +| **selfTestAD7280A!** | Performs the self test for both AD7280A devices on the board (one master and one slave). | 
 +| **alertPinAD7280A?​** | Reads the status of Alert Pin from AD7280A. | 
 +| **enableAD8280=** | Enables/​disables the AD8280 device. Accepted values:​\\ ​- disable the AD8280 device\\ 1 - enable the AD8280 device | 
 +| **alarmPinOvAD8280?​** | Reads the status of Overvoltage Alarm Pin from AD8280. | 
 +| **alarmPinUvAD8280?​** | Reads the status of Undervoltage Alarm Pin from AD8280. | 
 +| **selfTestAD8280!** | Performs the self test for both AD8280 devices on the board (one master and one slave)|
  
-**Section F** is used to configure the //Cell Balance timers// registers. By default the timers are set to 0. 
  
-**Section G** is used to configure ​the //Power Down timer//. By default the timer is set to 0.+Commands can be executed using a serial terminal connected ​to the UART peripheral of Xilinx KC705 FPGA.
  
-===== Troubleshooting =====+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :​resources:​fpga:​xilinx:​interposer:​Terminal_KC705.jpg?​ }}
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +===== Software Project Setup ===== 
-  * Check that the evaluation board is powered as instructed in the board'​s user guide. +{{page>​import_workspace}}
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//​**. +
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+
  
 ====== More information ====== ====== More information ======
   * [[resources:​tools-software:​linux-drivers:​iio-adc:​ad7887|AD7887 IIO ADC Linux Driver]]   * [[resources:​tools-software:​linux-drivers:​iio-adc:​ad7887|AD7887 IIO ADC Linux Driver]]
 {{page>​ez_common}} {{page>​ez_common}}
resources/fpga/xilinx/interposer/cn0235.txt · Last modified: 20 Jan 2014 15:01 by LucianS