This version is outdated by a newer approved version.
This version (26 Mar 2012 11:26) is a draft.
Approvals: 0/1
This version (26 Mar 2012 11:26) is a draft.Approvals: 0/1
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Table of Contents
CN0203 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design
Supported Devices
Evaluation Boards
Overview
This document presents the steps to setup an environment for using the EVAL-CN0203-SDPZ evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the Micrium µC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-CN0203-SDPZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices System Demonstration Platform (SDP). The SDP consists of a:
- a controller board, like the EVAL-SDP-CB1Z (SDP-B)
- an compatible Analog Devices SDP product evaluation board
- corresponding PC software
The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-CN0203-SDPZ Evaluation Board.
The EVAL-CN0203-SDPZ board provides a full function, high voltage (up to 44 V), flexible, programmable analog output solution that meets most requirements for programmable logic controller (PLC) and distributed control system (DCS) applications. When using this evaluation board with the SDP board or BeMicro SDK board, apply +6 V and GND to Connector CN2, 12-50 V and GND to Connector CN3.
The AD5620/AD5640/AD5660, members of the nanoDAC™ family of devices, are low power, single, 12-/14-/16-bit, buffered voltage-out DACs and are guaranteed monotonic by design. The adi>AD5620/adi>AD5640/adi>AD5660-1 parts include an internal, 1.25 V, 5 ppm/°C reference, giving a full-scale output voltage range of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output voltage range of 5 V. The reference associated with each part is available at the VREFOUT pin. The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2) or midscale (AD5620-3 and AD5660-3) and remains there until a valid write takes place. The parts contain a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The power consumption is 2.5 mW at 5 V, reducing to 1 µW in power-down mode. The AD5620/AD5640/AD5660 on-chip precision output amplifier allows rail-to-rail output swing to be achieved. For remote sensing applications, the output amplifier’s inverting input is available to the user. The AD5620/AD5640/AD5660 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards.
The AD5750/AD5750-1 are single-channel, low cost, precision voltage/current output drivers with hardware- or software- programmable output ranges. The software ranges are configured via an SPI-/MICROWIRE™-compatible serial interface. The AD5750/AD5750-1 target applications in PLC and industrial process control. The analog input to the AD5750/AD5750-1 is provided from a low voltage, single-supply digital-to-analog converter (DAC) and is internally conditioned to provide the desired output current/voltage range. Analog input ranges available are 0 V to 2.5 V (AD5750-1) or 0 V to 4.096 V (AD5750). The output current range is programmable across five current ranges: 4 mA to 20 mA, 0 mA to 20 mA or 0 mA to 24 mA, ±20 mA, and ±24 mA. An overrange of 2% is available on the unipolar current ranges. Voltage output is provided from a separate pin that can be configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V output ranges. An overrange of 20% is available on the voltage ranges. Analog outputs are short-circuit and open-circuit protected and can drive capacitive loads of 1 µF and inductive loads of 0.1 H. The device is specified to operate with a power supply range from ±12 V to ±24 V. Output loop compliance is 0 V to AVDD - 2.75 V. The flexible serial interface is SPI and MICROWIRE compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. The interface also features an optional PEC error checking feature using CRC-8 error checking, useful in industrial environments where data communication corruption can occur. The device also includes a power-on reset function, ensuring that the device powers up in a known state (0 V or tristate), and an asynchronous CLEAR pin that sets the outputs to zero scale/midscale voltage output or the low end of the selected current range. An HW SELECT pin is used to configure the part for hardware or software mode on power-up.
More information
- CN0203 Product Info - pricing, samples, datasheet
- AD5660 Product Info - pricing, samples, datasheet
- AD5750 Product Info - pricing, samples, datasheet
Getting Started
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Required Hardware
- FMC-SDP adapter board
- EVAL-CN0203-SDPZ evaluation board
Required Software
- Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
- uC-Probe run-time monitoring tool
Downloads
The following table presents a short description the reference design archive contents.
| Folder | Description |
|---|---|
| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. |
| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. |
| Software | Contains the source files of the software project that will be run by the Microblaze processor. |
| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. |
Run the Demonstration Project
Hardware Setup
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
- Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
- Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
- Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Kintex 7 device (see screenshot below).
- Program the KC705 FPGA using the “Bit/download.bit” file provided in the reference design archive.
- Power the ADI evaluation board.
At this point everything is set up and it is possible to start the evaluation of the ADI hardware through the controls in the uC-Probe application provided in the reference design.
Configure uC-Probe
Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.
Select uC-Probe options.
- Click on the uC-Probe icon on the top left portion of the screen.
- Click on the Options button to open the dialog box.
Set target board communication protocol as RS-232
- Click on the Communication tab icon on the top left portion of the dialog box
- Select the RS-232 option.
Setup RS-232 communication settings
- Select the RS-232 option from the Communication tab.
- Select the COM port to which the KC705 board is connected.
- Set the Baud Rate to 115200 bps.
- Press Apply and OK to exit the options menu.
Load and Run the Demonstration Project
- Click the Open option from the uC-Probe menu and select the .wsp file from the ucProbeInterface folder provided within the reference design files.
- Before opening the interface uC-Probe will ask for a symbols file that must be associated with the interface. Select the file ucProbeInterface/ADIEvalBoard.elf to be loaded as a symbol file.
- Run the demonstration project by pressing the Play button.
- In some cases it is possible that the uC-Probe interface will not respond to the commands the first time it is ran. In this situation just stop the interface by pressing the Stop button and run it again by pressing the Play button.
- After starting the uC-Probe interface wait until the status of the connection with the board displayed on the bottom of the screen is set to Connected. It is possible to use the interface only after the status is changed to Connected and the data transfer speed displayed next to the connection status is different than 0.
Demonstration Project User Interface
The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-CN0203-SDPZ evaluation board.
Section A is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board. See the Troubleshooting section for indications on how to fix the communication problems.
Section B is used to load a digital value to AD5660-1.
Section C is used to display the state of the error bits.
Section D is used to toggle the Clear Pin and to specify the JP1 position.
Section E is used to modify the output range.
Troubleshooting
In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues:
- Check that the evaluation board is powered as instructed in the board's user guide.
- In uC-Probe refresh the symbols file by right-clicking on the System Browser window and selecting Refresh Symbols.
- If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.
More information
resources/fpga/xilinx/interposer/cn0203.1332753978.txt.gz · Last modified: 26 Mar 2012 11:26 by Dragos Bogdan