This document presents the steps to setup an environment for using the EVAL-CN0203-SDPZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-CN0203-SDPZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-CN0203-SDPZ Evaluation Board.
The EVAL-CN0203-SDPZ board provides a full function, high voltage (up to 44 V), flexible, programmable analog output solution that meets most requirements for programmable logic controller (PLC) and distributed control system (DCS) applications. When using this evaluation board with the SDP board or BeMicro SDK board, apply +6 V and GND to Connector CN2, 12-50 V and GND to Connector CN3.
The AD5620/AD5640/AD5660, members of the nanoDAC™ family of devices, are low power, single, 12-/14-/16-bit, buffered voltage-out DACs and are guaranteed monotonic by design. The adi>AD5620/adi>AD5640/adi>AD5660-1 parts include an internal, 1.25 V, 5 ppm/°C reference, giving a full-scale output voltage range of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output voltage range of 5 V. The reference associated with each part is available at the VREFOUT pin. The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2) or midscale (AD5620-3 and AD5660-3) and remains there until a valid write takes place. The parts contain a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The power consumption is 2.5 mW at 5 V, reducing to 1 µW in power-down mode. The AD5620/AD5640/AD5660 on-chip precision output amplifier allows rail-to-rail output swing to be achieved. For remote sensing applications, the output amplifier’s inverting input is available to the user. The AD5620/AD5640/AD5660 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards.
The AD5750/AD5750-1 are single-channel, low cost, precision voltage/current output drivers with hardware- or software- programmable output ranges. The software ranges are configured via an SPI-/MICROWIRE™-compatible serial interface. The AD5750/AD5750-1 target applications in PLC and industrial process control. The analog input to the AD5750/AD5750-1 is provided from a low voltage, single-supply digital-to-analog converter (DAC) and is internally conditioned to provide the desired output current/voltage range. Analog input ranges available are 0 V to 2.5 V (AD5750-1) or 0 V to 4.096 V (AD5750). The output current range is programmable across five current ranges: 4 mA to 20 mA, 0 mA to 20 mA or 0 mA to 24 mA, ±20 mA, and ±24 mA. An overrange of 2% is available on the unipolar current ranges. Voltage output is provided from a separate pin that can be configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V output ranges. An overrange of 20% is available on the voltage ranges. Analog outputs are short-circuit and open-circuit protected and can drive capacitive loads of 1 µF and inductive loads of 0.1 H. The device is specified to operate with a power supply range from ±12 V to ±24 V. Output loop compliance is 0 V to AVDD - 2.75 V. The flexible serial interface is SPI and MICROWIRE compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. The interface also features an optional PEC error checking feature using CRC-8 error checking, useful in industrial environments where data communication corruption can occur. The device also includes a power-on reset function, ensuring that the device powers up in a known state (0 V or tristate), and an asynchronous CLEAR pin that sets the outputs to zero scale/midscale voltage output or the low end of the selected current range. An HW SELECT pin is used to configure the part for hardware or software mode on power-up.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
The following commands were implemented in this version of EVAL-CN0203 reference project for Xilinx KC705 FPGA board.
|help?||Displays all available commands.|
|register=|| Write a value to the DAC register. Accepted values:
0 .. 65535 - value to be written in register.
|register?||Displays the last value written to the DAC register.|
|ad5750clrPin=|| Sets the output value of CLR pin. Accepted values:
0 - sets the CLR pin low.(default)
1 - sets the CLR pin high.
|ad5750clrPin?||Displays the output value of CLR pin.|
|addressA0=|| Sets the value of A0 address bit(JP1). Accepted values:
0 - address is 0b000.(default)
1 - address is 0b001.
|addressA0?||Displays the value of A0 address bit(JP1).|
|range=|| Sets the output range for AD5750. Accepted values:
0 → 0V to 5V.
1 → 0V to 6V.
2 → 0V to 10V.
3 → 0V to 12V.
4 → -2.5V to +2.5V.
5 → -5V to +5V.
6 → -6V to +6V.
7 → -10V to +10V.
8 → -12V to +12V.
9 → 4mA to 20mA(internal).
10 → 4mA to 20mA(external).
11 → 0mA to 20mA(internal).
12 → 0mA to 20mA(external).
13 → 0mA to 24mA(internal).
14 → 0mA to 24mA(external).
15 → -20mA to +20mA(internal).
16 → -20mA to +20mA(external).
17 → -24mA to +24mA(internal).
18 → -24mA to +24mA(external).
19 → 3.92mA to 20.4mA(internal).
20 → 0mA to 20.4mA(internal).
21 → 0mA to 24.5mA(internal).
|range?||Displays the current output range.|
|fault?||Displays the list of possible faults.|
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design: