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resources:fpga:xilinx:interposer:cn0202 [16 Nov 2012 17:36]
larsc [Evaluation Boards]
resources:fpga:xilinx:interposer:cn0202 [04 Dec 2013 10:05] (current)
LucianS changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>​EVAL-CN0202-SDPZ|EVAL-CN0202-SDPZ]]** evaluation board together with the Xilinx KC705 FPGA boardthe Xilinx Embedded Development Kit (EDK) and the [[http://​micrium.com/​page/​products/​tools/​probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-CN0202-SDPZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>​EVAL-CN0202-SDPZ|EVAL-CN0202-SDPZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-CN0202-SDPZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :​resources:​fpga:​xilinx:​interposer:​cn0202.jpg?​600 }} {{ :​resources:​fpga:​xilinx:​interposer:​cn0202.jpg?​600 }}
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   * [[adi>/​static/​imported-files/​circuit_notes/​CN0202.pdf|EVAL-CN0202-SDPZ evaluation board user guide]]   * [[adi>/​static/​imported-files/​circuit_notes/​CN0202.pdf|EVAL-CN0202-SDPZ evaluation board user guide]]
   * [[http://​www.xilinx.com/​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://​www.xilinx.com/​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://​micrium.com/​page/​products/​tools/​probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack)+  * Xilinx ISE 14.6
-  * [[http://micrium.com/​page/​products/​tools/​probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal),​ baud rate 115200. 
 +  * The EVAL-CN0202 reference project for Xilinx KC705 FPGA. 
  
 ===== Downloads ===== ===== Downloads =====
- +<WRAP round download 80%> 
-  * {{:resources:fpga:xilinx:interposer:​cn0202_evalboard.zip|Reference Design Files}} +\\ 
- +  * **AD5662 Driver:** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/​device_drivers/​AD5662 
-The following table presents a short description the reference design archive contents. +  * **AD5750 Driver:** https://github.com/​analogdevicesinc/​no-OS/​tree/​master/​device_drivers/​AD5750 
- +  * **CN0202 Commands:** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/​device_commands/​CN0202 
-**Folder** **Description** +  ​* **Xilinx Boards Common Drivers:** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/​platform_drivers/​Xilinx/​SDP_Common 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation| +  * **EDK KC705 Reference ​project:** https://​github.com/​analogdevicesinc/​fpgahdl_xilinx/​tree/​master/​cf_sdp_kc705 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +\\ 
-| Software | Contains the source files of the software ​project ​that will be run by the Microblaze processor.| +</​WRAP>​
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. | +
 ====== Run the Demonstration Project ====== ====== Run the Demonstration Project ======
  
-{{page>​ucprobe_common}} +===== Hardware setup =====
- +
-===== Demonstration Project User Interface ​===== +
- +
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-CN0202-SDPZ** evaluation board. +
- +
-{{ :​resources:​fpga:​altera:​bemicro:​cn0202_interface.png?​600 }} +
- +
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//​ON/​OFF//​** switch. The **//​Activity//​** LED turns green when the communication is active. If the **//​ON/​OFF//​** switch is set to **//ON//** and the **//​Activity//​** LED is **//​BLACK//​** it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. +
- +
-**Section B** is used to load a digital value to AD5662.+
  
-**Section C** is used to display ​the state of the error bits.+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage ​of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</​WRAP>​
  
-**Section D** is used to toggle ​the Clear Pin and to specify ​the JP1 position.+  ​Use the FMC-SDP interposer ​to connect ​the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables ​to the KC705 and power up the FPGA board.
  
-**Section E** is used to modify ​the output range.+===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-CN0202 reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +**help?** | Displays all available commands. | 
 +| **register=** | Write a value to the DAC register. Accepted values:\\ 0 .. 65535 - value to be written in register. | 
 +| **register?​** | Displays the last value written to the DAC register. | 
 +| **ad5750clrPin=** | Sets the output value of CLR pin. Accepted values:\\ 0 - sets the CLR pin low.(default)\\ 1 - sets the CLR pin high. | 
 +| **ad5750clrPin?​** | Displays the output value of CLR pin. | 
 +| **addressA0=** | Sets the value of A0 address bit(JP1). Accepted values:\\ 0 - address ​is 0b000.(default)\\ 1 - address is 0b001. | 
 +| **addressA0?​** | Displays the value of A0 address bit(JP1). | 
 +| **range=** | Sets the output range for AD5750. Accepted values:\\ 0 -> 0V to 5V.\\ 1 -> 0V to 6V.\\ 2 -> 0V to 10V.\\ 3 -> 0V to 12V.\\ 4 -> -2.5V to +2.5V.\\ 5 -> -5V to +5V.\\ 6 -> -6V to +6V.\\ 7 -> -10V to +10V.\\ 8 -> -12V to +12V.\\ 9 ->  4mA to 20mA(internal).\\ 10 -> 4mA to 20mA(external).\\ 11 -> 0mA to 20mA(internal).\\ 12 -> 0mA to 20mA(external).\\ 13 -> 0mA to 24mA(internal).\\ 14 -> 0mA to 24mA(external).\\ 15 -> -20mA to +20mA(internal).\\ 16 -> -20mA to +20mA(external).\\ 17 -> -24mA to +24mA(internal).\\ 18 -> -24mA to +24mA(external).\\ 19 -> 3.92mA to 20.4mA(internal).\\ 20 -> 0mA to 20.4mA(internal).\\ 21 -> 0mA to 24.5mA(internal). | 
 +| **range?** | Displays ​the current ​output range. | 
 +| **fault?** | Displays the list of possible faults. | 
 +  
 +Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
  
-===== Troubleshooting =====+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :​resources:​fpga:​xilinx:​interposer:​Terminal_KC705.jpg?​ }}
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +===== Software Project Setup ===== 
-  * Check that the evaluation board is powered as instructed in the board'​s user guide. +{{page>​import_workspace}}
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//​**. +
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+
  
 ====== More information ====== ====== More information ======
   * [[resources:​tools-software:​linux-drivers:​iio-dac:​ad5446|AD5662 IIO DAC Linux Driver]]   * [[resources:​tools-software:​linux-drivers:​iio-dac:​ad5446|AD5662 IIO DAC Linux Driver]]
 {{page>​ez_common}} {{page>​ez_common}}
resources/fpga/xilinx/interposer/cn0202.txt · Last modified: 04 Dec 2013 10:05 by LucianS