This document presents the steps to setup an environment for using the EVAL-CN0194-SDPZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-CN0194-SDPZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-CN0194-SDPZ Evaluation Board.
The EVAL-CN0194-SDPZ board provides galvanic isolation for high speed, high accuracy, simultaneous sampling analog-to-digital conversion applications. The 16-bit AD7685 PulSAR ADC is versatile and allows monitoring of multiple channels through daisy chaining. When using this evaluation board with the SDP board or BeMicro SDK board, connect a +6 V power supply to the pins marked “+6V CFTL” and “+6 V SDP” on the board.
The AD7685 is a 16-bit, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN-. The reference voltage, REF, is applied externally and can be set up to the supply voltage.
Power dissipation scales linearly with throughput.
The SPI-compatible serial interface also features the ability, using the SDI input, to daisy chain several ADCs on a single 3-wire bus or provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate supply VIO.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
The following commands were implemented in this version of EVAL-CN0194 reference project for Xilinx KC705 FPGA board.
|help?||Displays all available commands.|
|adcCode?|| Displays the ADC Code for selected channel. Accepted values:
1 - channel 1.
2 - channel 2.
|voltage?|| Displays the input voltage for selected channel. Accepted values:
1 - channel 1.
2 - channel 2.
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral.
The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design: