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Files in resources:eval:user-guides:ade9430_trm
- 3-wire_delta_normal_phase_sequence.svg
- 26 Apr 2022 22:49
- 10.2 KB
- 3-wire_delta_phase_b_connected_to_ground.svg
- 19 Nov 2021 19:51
- 37.6 KB
- 3-wire_delta_phase_sequence_error_wiring_error.svg
- 30 Nov 2021 20:19
- 16.7 KB
- 3-wire_delta_series_impedance_on_phase_b_and_vconsel_100_-_copy.svg
- 26 Apr 2022 22:57
- 31 KB
- 3-wire_delta_service_vector_diagram.svg
- 17 Nov 2021 21:43
- 5 KB
- 3-wire_network_meter_vector_diagram.svg
- 17 Nov 2021 21:45
- 4.9 KB
- 3-wire_residential_1ph_service_vector_diagram.svg
- 17 Nov 2021 21:52
- 4.8 KB
- 4-wire_wye_and_4-wire_delta_normal_phase_sequence.svg
- 15 Nov 2021 22:55
- 14.1 KB
- 4-wire_wye_and_4-wire_delta_phase_sequence_error_wiring_error_.svg
- 15 Nov 2021 22:55
- 12.6 KB
- 4-wire_wye_neutral_connected_to_ground.svg
- 19 Nov 2021 19:28
- 43.1 KB
- 4-wire_wye_series_impedance_on_the_neutral.svg
- 19 Nov 2021 19:29
- 48.5 KB
- 4-wire_wye_service_vector_diagram.svg
- 17 Nov 2021 21:42
- 5.3 KB
- 4-wire_wye_voltage_phase_sequence_in_time.svg
- 17 Nov 2021 21:46
- 11.1 KB
- 15210-001-mod.svg
- 04 Nov 2021 19:28
- 58.5 KB
- 15523-002.svg
- 04 Nov 2021 20:40
- 74 KB
- 15523-003.svg
- 04 Nov 2021 19:57
- 8.5 KB
- 15523-004.svg
- 04 Nov 2021 21:10
- 35.8 KB
- 15523-005.svg
- 04 Nov 2021 21:10
- 35.1 KB
- 15523-006.svg
- 04 Nov 2021 21:10
- 35.7 KB
- adc_redirect_modulator_to_digital_datapath_multiplexing.svg
- 09 Nov 2021 18:35
- 3.1 MB
- ade9000_multipointcalibration.svg
- 09 Nov 2021 18:56
- 10 KB
- ade9430_power_on_sequence_for_psm0.svg
- 05 Nov 2021 15:28
- 117 KB
- awatt_accumulation_into_energy_and_power_using_no-load_threshold_and_signed_accumulation_mode.svg
- 09 Nov 2021 22:37
- 31.8 KB
- combined_zero_crossing_detection.svg
- 10 Nov 2021 21:55
- 33 KB
- command_header_cmd_hdr.svg
- 17 Nov 2021 17:16
- 3.3 KB
- connecting_the_ade9430_slave_spi_port_to_a_master_spi_device.svg
- 17 Nov 2021 17:33
- 3 KB
- crc_calculation_of_16-bit_spi_data.svg
- 17 Nov 2021 19:39
- 5.4 KB
- crc_calculation_of_32-bit_spi_data.svg
- 17 Nov 2021 19:37
- 6.6 KB
- crystal_application_circuit.svg
- 05 Nov 2021 15:20
- 39.7 KB
- data_path_following_adc_stage.svg
- 05 Nov 2021 14:52
- 36.4 KB
- egyrdy_and_pwrrdy_update_rate.svg
- 09 Nov 2021 22:59
- 12.5 KB
- fixed_data_rate_waveform_sample_storage.svg
- 17 Nov 2021 19:52
- 6.6 KB
- fundamental_apparent_power_afva.svg
- 09 Nov 2021 19:58
- 5 KB
- fundamental_reactive_power_afvar.svg
- 09 Nov 2021 19:29
- 7.2 KB
- fundamental_watt_afwatt_calculation.svg
- 09 Nov 2021 19:25
- 7.6 KB
- instantaneous_active_power_and_low-pass_filtered_active_power_at_a_power_factor_of_1.svg
- 09 Nov 2021 19:02
- 15.5 KB
- internal_energy_register_to_awatthr_hi_and_awatthr_lo.svg
- 09 Nov 2021 22:59
- 13 KB
- internal_power_register_to_awatt_acc.svg
- 10 Nov 2021 19:58
- 7.1 KB
- lfsr_generator_used_for_crc_spi_calculation.svg
- 17 Nov 2021 19:39
- 15.6 KB
- line_period_calculation_using_zero_crossing_detection_and_linear_interpolation.svg
- 15 Nov 2021 21:30
- 9.7 KB
- no-load_detection_and_indication.svg
- 09 Nov 2021 22:49
- 21.3 KB
- non-blondel_compliant_3-wire_delta.svg
- 19 Nov 2021 20:00
- 42 KB
- non-blondel_compliant_4-wire_wye.svg
- 19 Nov 2021 19:58
- 41.9 KB
- per_phase_power_and_energy_calculations_from_xi_pcf_and_xv_pcf_waveforms.svg
- 09 Nov 2021 22:28
- 12.3 KB
- phase_compensation_example_for_current_transformer_where_the_current_leads_the_voltage.svg
- 09 Nov 2021 18:46
- 21.3 KB
- phase_compensation_example_where_current_lags_voltage.svg
- 09 Nov 2021 18:51
- 21 KB
- power_accumulation_and_power_sign.svg
- 10 Nov 2021 21:56
- 61.3 KB
- resampled_waveform_sample_storage.svg
- 17 Nov 2021 21:08
- 7.5 KB
- spi_read_protocol_example_crc_or_next_data_can_follow.svg
- 17 Nov 2021 17:14
- 17.3 KB
- spi_read_protocol_example_where_the_following_data_is_the_crc_or_the_initial_data_is_repeated.svg
- 17 Nov 2021 17:38
- 21.4 KB
- spi_write_protocol_example.svg
- 17 Nov 2021 17:15
- 11.1 KB
- temperature_measurement_block_diagram.svg
- 17 Nov 2021 16:56
- 2.4 KB
- voltage_to_current_phase_angles.svg
- 15 Nov 2021 21:50
- 8.1 KB
- voltage_to_voltage_phase_angle.svg
- 15 Nov 2021 21:50
- 10.3 KB
- watt_and_var_sign_for_capacitive_and_inductive_loads.svg
- 17 Nov 2021 16:49
- 8.8 KB
- waveform_buffer_spi_burst_read_of_resampled_data_with_burst_chan_0011.svg
- 17 Nov 2021 21:22
- 26 KB
- waveform_buffer_spi_single_address_read_of_fixed_rate_data_with_burst_chan_1111.svg
- 17 Nov 2021 21:23
- 21.3 KB
- waveform_buffer_spi_single_address_read_of_resampled_data_with_burst_chan_1111.svg
- 17 Nov 2021 21:24
- 22.9 KB
- zero-crossing_output_rates.svg
- 10 Nov 2021 22:07
- 14.6 KB
- zero_crossing_detection_on_voltage_and_current_channels.svg
- 10 Nov 2021 21:55
- 11.4 KB
![[root]](/resources/fpga/xilinx/interposer/cn0188?ns=&tab_files=files&do=media&tab_details=view&image=resources%3Aeval%3Auser-guides%3Axbdp-wiki-system-block-diagram.png){kind=link}
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- Date:
- 23 May 2022 13:24
- Filename:
- xbdp-wiki-system-block-diagram.png
- Format:
- PNG
- Size:
- 380KB
- Width:
- 3018
- Height:
- 941
- References for:
- X-Band Phased Array Development Platform User Guide
resources/fpga/xilinx/interposer/cn0188.txt · Last modified: 09 Jan 2021 00:49 by Robin Getz