This document presents the steps to setup an environment for using the EVAL-CN0150A-SDPZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-CN0150A-SDPZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices System Demonstration Platform (SDP). The SDP consists of a:
The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-CN0150A-SDPZ Evaluation Board.
The CN0150 circuit measures RF power at any frequency from 1 MHz to 8 GHz over a range of approximately 60 dB. The measurement result is provided as a digital code at the output of a 12-bit ADC with serial interface and integrated reference. The output of the RF detector has a glueless interface to the ADC and uses most of the ADC’s input range without further adjustment. A simple two-point system calibration is performed in the digital domain.
The AD8318 maintains accurate log conformance for signals of 1 MHz to 6 GHz and provides useful operation to 8 GHz. The device provides a typical output voltage temperature stability of ±0.5 dB.
The AD7887 ADC can be configured for either dual or single channel operation via the on-chip control register. There is a default single-channel mode that allows the AD7887 to be operated as a read-only ADC, thereby simplifying the control logic.
The EVAL-CN0150A-SDPZ board contains the circuit to be evaluated, as described in this note. To power the EVAL-CN0150A-SDPZ evaluation board supply +6V between the +6 V and GND inputs.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
The following commands were implemented in this version of EVAL-CN0150 reference project for Xilinx KC705 FPGA board.
|help?||Displays all available commands.|
|calibration=|| Makes a two points calibration. Accepted values:
-50 .. -5 - first point input power in [dBm].
-50 .. -5 - second point input power in [dBm].
|pinCalc?||Displays the calculated input power in [dBm].|
|error?|| Displays the error associated with the last input power calculation. Accepted values:
-50 .. -5 - true input power in [dBm].
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design: