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resources:fpga:xilinx:interposer:adf4157 [28 May 2012 15:53]
Alexandru.Tofan Approved
resources:fpga:xilinx:interposer:adf4157 [04 Nov 2013 09:21]
LucianS changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact
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 ====== Overview ====== ====== Overview ======
-This document presents the steps to setup an environment for using the **[[http://​​en/​rfif-components/​pll-synthesizersvcos/​adf4157/​products/​EVAL-ADF4157/​eb.html|EVAL-ADF4157SD1Z]]** evaluation board together with the Xilinx KC705 FPGA boardthe Xilinx Embedded Development Kit (EDK) and the [[http://​​page/​products/​tools/​probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-ADF4157SD1Z Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[http://​​en/​rfif-components/​pll-synthesizersvcos/​adf4157/​products/​EVAL-ADF4157/​eb.html|EVAL-ADF4157SD1Z]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-ADF4157SD1Z Evaluation Board with the Xilinx KC705 board.
 {{ :​resources:​fpga:​xilinx:​interposer:​img_adf4156.jpg?​400 }} {{ :​resources:​fpga:​xilinx:​interposer:​img_adf4156.jpg?​400 }}
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   * [[http://​​servlet/​JiveServlet/​download/​26680-6443/​EVAL-ADF4157_revPrA.pdf|EVAL-ADF4157SD1Z evaluation board user guide]]   * [[http://​​servlet/​JiveServlet/​download/​26680-6443/​EVAL-ADF4157_revPrA.pdf|EVAL-ADF4157SD1Z evaluation board user guide]]
   * [[http://​​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://​​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://​​page/​products/​tools/​probe|Micrium uC-Probe]] 
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack)+  * Xilinx ISE 14.6
-  * [[​page/​products/​tools/​probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal),​ baud rate 115200. 
 +  * The EVAL-ADF4157 reference project for Xilinx KC705 FPGA. 
 ===== Downloads ===== ===== Downloads =====
- +<WRAP round download 80%> 
-  * {{:resources:​fpga:xilinx:​interposer:​|Reference Design Files}} +\\ 
- +  * **ADF4157 Driver:**​analogdevicesinc/​no-OS/​tree/​master/​device_drivers/​ADF4157 
-The following table presents a short description the reference design archive contents. +  * **ADF4157 Commands:** https://​​analogdevicesinc/​no-OS/​tree/​master/​device_commands/​ADF4157 
- +  ​* **Xilinx Boards Common Drivers:** https://​​analogdevicesinc/​no-OS/​tree/​master/​platform_drivers/​Xilinx/​SDP_Common 
-**Folder** **Description** +  * **EDK KC705 Reference ​project:** https://​​analogdevicesinc/​fpgahdl_xilinx/​tree/​master/​cf_sdp_kc705 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation| +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +</​WRAP>​
-| Software | Contains the source files of the software ​project ​that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | +
 ====== Run the Demonstration Project ====== ====== Run the Demonstration Project ======
-{{page>​ucprobe_common}} +===== Hardware setup =====
- +
-===== Demonstration Project User Interface ​===== +
- +
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-ADF4157SD1Z** evaluation board. +
- +
-{{ :​resources:​fpga:​xilinx:​interposer:​adf4157interface.jpg?​700 | ucProbe Interface }} +
- +
-**Section A** allows turning the communication with the Evaluation Board ON or OFF by toggling the switch. The green LED on the switch will turn on when communication is active. Before pressing the //ON/OFF// switch, make sure you select the desired //Device Initialization Procedure//​. If the //ON/OFF// switch is set to ON and the //​Activity//​ LED is BLACK it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems.+
-**Section B** allows controlling ​the output on MUXOUTSet to for DVdd, 2 for GND or 7 for SDO (can be used to test if communication with board is active).+<WRAP round important 80%> 
 +Before connecting ​the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting ​for VADJ_FPGA visit the Xilinx KC705 product page. 
-**Section C** allows setting Fractional, Integer, Current, R Counter ​and Clock Divider Values. See pg. 18 of datasheet for calculated examples of these values.+  ​Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  ​Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
-**Section D** allows setting or clearing certain control bits in Register R2 and R3See datasheet pg14-16 for details.+===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-ADF4157 reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +**help?** | Displays all available commands. | 
 +| **frequency=** | Sets the desired output frequency ​in MHzAccepted values:\\ 500 ... 6000 desired output frequency in MHz. | 
 +| **frequency?​** | Displays the output frequency in MHz. | 
 +| **register=** | Sets the value of the desired register on 29 bits. Accepted values:\\ register:\\ 0 .. 4 - the selected register.\\ value:\\ 0 .. 0x1FFFFFFF - the new value of the register. | 
 +| **register?​** | Displays the value of the desired register. Accepted values:\\ 0 .. 4 - the selected register. | 
 +| **chsp?** | Displays the calculated channel spacing. | 
 +| **fract?** | Displays the calculated fractional value. | 
 +| **PFDfreq?​** | Displays the current PFD frequency in MHz
-**Section E** is used to apply settings. After setting everything as desired, press this button to send data to the ADF4157.+Commands can be executed using a serial terminal connected ​to the UART peripheral of Xilinx KC705 FPGA.
-===== Troubleshooting =====+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :​resources:​fpga:​xilinx:​interposer:​Terminal_KC705.jpg?​ }}
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +===== Software Project Setup ===== 
-  * Check that the evaluation board is powered as instructed in the board'​s user guide. +{{page>​import_workspace}}
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//​**. +
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+
 ====== More information ====== ====== More information ======
 {{page>​ez_common}} {{page>​ez_common}}
resources/fpga/xilinx/interposer/adf4157.txt · Last modified: 22 Jul 2019 14:12 by AndreiD1994