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resources:fpga:xilinx:interposer:adf4001 [28 May 2012 15:53] – Approved Alexandru.Tofan | resources:fpga:xilinx:interposer:adf4001 [09 Jan 2021 00:49] (current) – user interwiki links Robin Getz | ||
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===== Evaluation Boards ===== | ===== Evaluation Boards ===== | ||
- | * [[adi> | + | * [[adi>EVAL-ADF4001|EVAL-ADF4001SD1Z]] |
====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
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* [[adi> | * [[adi> | ||
* [[adi>/ | * [[adi>/ | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
- | * [[http:// | + | |
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Hardware ===== | ===== Required Hardware ===== | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
* FMC-SDP adapter board | * FMC-SDP adapter board | ||
* **EVAL-ADF4001SD1Z** evaluation board | * **EVAL-ADF4001SD1Z** evaluation board | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
===== Downloads ===== | ===== Downloads ===== | ||
+ | <WRAP round download 80%> | ||
+ | \\ | ||
+ | * **ADF4001 Driver:** https:// | ||
+ | * **ADF4001 Commands:** https:// | ||
+ | * **Xilinx Boards Common Drivers:** https:// | ||
+ | * **EDK KC705 Reference project:** https:// | ||
+ | \\ | ||
+ | </ | ||
- | * {{: | + | ===== Hardware setup ===== |
- | The following table presents a short description | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting | ||
+ | </ | ||
- | ^ **Folder** ^ **Description** ^ | + | |
- | | Bit | Contains | + | * Connect |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | |
- | | Software | Contains the source files of the software project that will be run by the Microblaze processor.| | + | |
- | | uCProbeInterface | Contains | + | |
- | ====== Run the Demonstration | + | ===== Reference |
+ | The following commands were implemented in this version of EVAL-ADF4001SD1Z reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **setregister=** | Update the selected latch with the current set ups. Accepted value:\\ latch:\\ 0 - Reference latch\\ 1 - N Counter Latch\\ 2 - Function Latch\\ 3 - Initialization Latch\\ value:\\ 24 bit values, you can find more information about the registers in the data sheet | | ||
+ | | **getregister? | ||
+ | | **setfrequency=** | Set the VCO frequency. Accepted value:\\ 5 .. 200 - betwwen 5Mhz and 200Mhz | | ||
+ | | **getfrequency? | ||
- | {{page> | + | Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. |
- | ===== Demonstration Project User Interface ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-ADF4001SD1Z** evaluation board. | + | ===== Software Project Setup ===== |
- | + | {{page> | |
- | {{ : | + | |
- | + | ||
- | **Section A** allows for the communication with the board to be activated / deactivated by toggling the //ON/OFF// switch. The // | + | |
- | The //Error// LED will indicate that the data received on the SDO pin is different than data sent. If the //Function Latch// or // | + | |
- | + | ||
- | **Sections B to E** allow for configuration of each latch on the **ADF4001**. | + | |
- | + | ||
- | **Section B** allows for the configuration of the //Reference Counter Latch//. The //LDP// switch will toggle on or off the //Lock Detect Precision// bits. The //TBS// and //ABW// sliders will configure the //Test Mode Bits// and //Anti Backlash Width// bits respectively. The //14 Bit Reference Counter// allows for the configuration of the counter. The last numerical display will display the resulting value in a decimal format. By toggling the //Write// switch in this section, a single write will be performed on the //Reference Counter Latch// with the programmed value. | + | |
- | + | ||
- | **Section C** allows for the configuration of the //N Counter Latch//. The //CPG// switch toggles the //CP Gain// bit. The //13 Bit N Counter// allows for the configuration of the N counter. The last numerical display in the row will display the resulting value in a decimal format. By toggling the //Write// switch, a single write will be performed on the //N Counter Latch//, with the value displayed. | + | |
- | + | ||
- | **Sections D and E** have the same structure. The difference between these two latches is that when the // | + | |
- | //PD2// switch toggles the //Power Down 2// pin. The //CS2// and //CS1// sliders will configure the //Current Setting 2// and //Current Setting 1// bits respectively. The //Timer Counter Control// can be configured through the //TCC// slider. Next, the switches configure the //Fastlock Mode//, //Fastlock Enable//, //CP Three-State// | + | |
- | + | ||
- | ===== Troubleshooting | + | |
- | + | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | |
- | * Check that the evaluation board is powered as instructed in the board' | + | |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
{{page> | {{page> |