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resources:fpga:xilinx:interposer:adf4001 [19 Nov 2012 18:56] – [Evaluation Boards] fix link Lars-Peter Clausenresources:fpga:xilinx:interposer:adf4001 [31 Oct 2013 10:54] – Fix some typos. Istvan Csomortani
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   * [[adi>EVAL-ADF4001|EVAL-ADF4001SD1Z]]   * [[adi>EVAL-ADF4001|EVAL-ADF4001SD1Z]]
 +
 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>ADF4001|EVAL-ADF4001SD1Z]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-ADF4001SD1Z Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>ADF4001|EVAL-ADF4001SD1Z]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-ADF4001SD1Z Evaluation Board with the Xilinx KC705 board.
  
 {{ :resources:fpga:xilinx:interposer:img_adf4001.jpg }} {{ :resources:fpga:xilinx:interposer:img_adf4001.jpg }}
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   * [[adi>/static/imported-files/user_guides/UG-092.pdf|EVAL-ADF4001SD1Z evaluation board user guide]]   * [[adi>/static/imported-files/user_guides/UG-092.pdf|EVAL-ADF4001SD1Z evaluation board user guide]]
   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.6. 
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200.
  
 ===== Downloads ===== ===== Downloads =====
 +<WRAP round download 80%>
 +\\
 +  * **ADF4001 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/ADF4106
 +  * **ADF4001 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/ADF4106
 +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common
 +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705
 +\\
 +</WRAP>
  
-  * {{:resources:fpga:xilinx:interposer:adf4001_evalboard.zip|Reference Design Files}} +===== Hardware setup =====
- +
-The following table presents a short description the reference design archive contents. +
- +
-^ **Folder** ^ **Description** ^ +
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | +
- +
-====== Run the Demonstration Project ====== +
- +
-{{page>ucprobe_common}} +
- +
-===== Demonstration Project User Interface ===== +
- +
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-ADF4001SD1Z** evaluation board. +
- +
-{{ :resources:fpga:altera:bemicro:adf4001interface.png?700 }} +
- +
-**Section A** allows for the communication with the board to be activated / deactivated by toggling the //ON/OFF// switch. The //Activity// LED turns green when the communication is active. Before pressing the //ON/OFF// switch, make sure you select the desired //Device Initialization Procedure//. If the //ON/OFF// switch is set to ON and the //Activity// LED is BLACK it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. +
-The //Error// LED will indicate that the data received on the SDO pin is different than data sent. If the //Function Latch// or //Initialization Latch// is written, with a different //MUXOUT// value than 6, this LED will be activated. To reset the LED, the board must be deactivated and reactivated, case in which the //Initialization procedure// will set //MUXOUT// to 6.+
  
-**Sections B to E** allow for configuration of each latch on the **ADF4001**.+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-**Section B** allows for the configuration of the //Reference Counter Latch//. The //LDP// switch will toggle on or off the //Lock Detect Precision// bits. The //TBS// and //ABW// sliders will configure the //Test Mode Bits// and //Anti Backlash Width// bits respectively. The //14 Bit Reference Counter// allows for the configuration of the counter. The last numerical display will display the resulting value in a decimal format. By toggling the //Write// switch in this section, a single write will be performed on the //Reference Counter Latch// with the programmed value.+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-**Section C** allows for the configuration of the //N Counter Latch//. The //CPG// switch toggles the //CP Gain// bit. The //13 Bit N Counter// allows for the configuration of the N counter. The last numerical display in the row will display the resulting value in a decimal format. By toggling the //Write// switch, a single write will be performed on the //N Counter Latch//, with the value displayed. +===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-ADF4001SD1Z reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **setregister=** | Update the selected latch with the current set ups. Accepted value:\\ latch:\\ 0 - Reference latch\\ 1 - N Counter Latch\\ 2 - Function Latch\\ 3 - Initialization Latch\\ value:\\ 24 bit values, you can find more information about the registers in the data sheet | 
 +| **getregister?** | Print the specified latch values in a human readable format. Accepted value:\\ latch:\\ 0 - Reference latch\\ 1 - N Counter Latch\\ 2 - Function Latch\\ 3 - Initialization Latch | 
 +| **setfrequency=** | Set the VCO frequency. Accepted value:\\ 5 .. 200 - betwwen 5Mhz and 200Mhz | 
 +| **getfrequency?** | Print the actual VCO frequency. |
  
-**Sections D and E** have the same structure. The difference between these two latches is that when the //Initialization Latch// is programmed, there is an additional internal reset pulse applied to the //R// and //N// counters. This pulse ensures that the //N counter// is at a load point when the //N counter// data is latched, and the device will begin counting in close phase alignment. +Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
-//PD2// switch toggles the //Power Down 2// pin. The //CS2// and //CS1// sliders will configure the //Current Setting 2// and //Current Setting 1// bits respectively. The //Timer Counter Control// can be configured through the //TCC// slider. Next, the switches configure the //Fastlock Mode//, //Fastlock Enable//, //CP Three-State// and //Phase Detector Polarity// bits. The //MUX// slider allows to select what is to be available on the //MUXOUT// pin. By default, at initialization, this has the value 6 set, in order to be able to use this pin as SDO. //PD1// switch allows for setting the //Power Down 1// bits. Lastly, the //CR// switch allows for resetting the //R// and //N// counters.+
  
-===== Troubleshooting =====+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }}
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +===== Software Project Setup ===== 
-  * Check that the evaluation board is powered as instructed in the board's user guide. +{{page>import_workspace}}
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. +
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+
  
 ====== More information ====== ====== More information ======
 {{page>ez_common}} {{page>ez_common}}
resources/fpga/xilinx/interposer/adf4001.txt · Last modified: 09 Jan 2021 00:49 by Robin Getz

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