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resources:fpga:xilinx:interposer:ad9837 [28 Sep 2012 13:39]
AdrianC Added common section for describing the evaluation setup and System Demonstration Platform
resources:fpga:xilinx:interposer:ad9837 [21 Oct 2013 15:22] (current)
LucianS changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>​AD9837|EVAL-AD9837SDZ]]** evaluation board together with the Xilinx KC705 FPGA boardthe Xilinx Embedded Development Kit (EDK) and the [[http://​micrium.com/​page/​products/​tools/​probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD9837SDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>​AD9837|EVAL-AD9837SDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD9837SDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :​resources:​fpga:​xilinx:​interposer:​img_ad9837.jpg }} {{ :​resources:​fpga:​xilinx:​interposer:​img_ad9837.jpg }}
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   * [[adi>/​static/​imported-files/​user_guides/​UG-269.pdf|EVAL-AD9837SDZ evaluation board user guide]]   * [[adi>/​static/​imported-files/​user_guides/​UG-269.pdf|EVAL-AD9837SDZ evaluation board user guide]]
   * [[http://​www.xilinx.com/​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://​www.xilinx.com/​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://​micrium.com/​page/​products/​tools/​probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack)+  * Xilinx ISE 14.6
-  * [[http://micrium.com/​page/​products/​tools/​probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal),​ baud rate 115200. 
 +  * The EVAL-AD9837 reference project for Xilinx KC705 FPGA. 
  
 ===== Downloads ===== ===== Downloads =====
- +<WRAP round download 80%> 
-  * {{:resources:​fpga:xilinx:​interposer:​ad9837_evalboard.zip|Reference Design Files}} +\\ 
- +  * **AD9837 Driver:** https://github.com/​analogdevicesinc/​no-OS/​tree/​master/​device_drivers/​AD9833 
-The following table presents a short description the reference design archive contents. +  * **AD9837 Commands:** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/​device_commands/​AD9833 
- +  ​* **Xilinx Boards Common Drivers:** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/​platform_drivers/​Xilinx/​SDP_Common 
-**Folder** **Description** +  * **EDK KC705 Reference ​project:** https://​github.com/​analogdevicesinc/​fpgahdl_xilinx/​tree/​master/​cf_sdp_kc705 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation| +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +</​WRAP>​
-| Software | Contains the source files of the software ​project ​that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | +
 ====== Run the Demonstration Project ====== ====== Run the Demonstration Project ======
  
-{{page>​ucprobe_common}} +===== Hardware setup =====
- +
-===== Demonstration Project User Interface ​===== +
- +
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD9837SDZ** evaluation board. +
- +
-{{ :​resources:​fpga:​altera:​bemicro:​ad9837interface.png?​700 }}+
  
-**Section A** is used to activate ​the board and monitor activity. The communication with the board is activated / deactivated by toggling ​the **//​ON/​OFF//​** switch. The **//​Activity//​** LED turns green when the communication is active. If the **//​ON/​OFF//​** switch ​is set to **//ON//** and the **//​Activity//​** LED is **//​BLACK//​** it means that there is a communication problem with the boardSee the **Troubleshooting** section for indications ​on how to fix the communication problems.+<WRAP round important 80%> 
 +\\ 
 +Before connecting ​the ADI evaluation ​board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details ​on how to change ​the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</​WRAP>​
  
-**Section B** is used to choose the frequency register, the phase register and the signal from the VOUT output. +  * Use the FMC-SDP interposer ​to connect ​the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector
-  * **//​Frequency control//​**:​ +  * Connect ​the JTAG and UART cables to the KC705 and power up the FPGA board.
-   * //F1// – FREQ1 register is used in the phase accumulator. +
-   * //F0// – FREQ0 register is used in the phase accumulator. +
-  * **//Phase control//​**:​ +
-   * //P1// – PHASE1 register data is added to the output of the phase accumulator. +
-   * //P0// – PHASE0 register data is added to the output of the phase accumulator+
-  * **//VOUT Output//​**:​ +
-   * //MSB// – MSB of the DAC at the output. +
-   * //MSB/2// – MSB/2 of the DAC at the output. +
-   * //​Triangle//​ – Triangle signal at the output. +
-   * //​Sinusoid//​ – Sinusoidal signal at the output.+
  
-**Section C** is used to load values ​in the frequency and phase registersfrequency value is set using the corresponding dial and slider controls The dial sets the number ​of the digit to be modified and the slider sets the value of the selected ​digitFor example ​in order to set the value of 1234 Hz the following steps have to be performed (not necessarily ​in the listed order):  +===== Reference Project Overview ===== 
-   ​put the dial to position ​and move the slider to 4 +The following commands were implemented in this version of EVAL-AD9837 reference project for Xilinx KC705 FPGA board. 
-   ​put the dial to position ​and move the slider to 3 +^ Command ^ Description ^ 
-   ​put the dial to position ​2 and move the slider to 2 +**help?** | Displays all available commands. | 
-   ​put the dial to position 3 and move the slider to 1+| **output=** | Selects the type of output. Accepted ​values:\\ 0 - Sinusoid.(default)\\ 1 - Triangle.\\ 2 - DAC Data MSB/2.\\ 3 - DAC Data MSB. | 
 +| **output?** | Displays ​the type of output
 +| **loadFreqReg=** | Loads a frequency value in one selected registerAccepted values:\\ Register ​number:\\ 0 - Frequency Register 0.\\ 1 - Frequency Register 1.\\ Value:\\ 0 .. 8 000 000 - the frequency ​value in Hz. | 
 +| **freqRegVal?​** | Displays ​the value from one selected ​frequency register ​Accepted values:\\ Register number:\\ 0 - Frequency Register 0.\\ 1 - Frequency Register 1. | 
 +| **loadPhaseReg=** | Loads a phase value in one selected register. Accepted values:\\ Register number:\\ 0 - Phase Register 0.\\ 1 - Phase Register 1.\\ Value:\\ 0 .. 2PI - the phase value in radians. | 
 +| **phaseRegVal?​** | Displays ​the value from one selected phase register. ​ Accepted values:\\ Register number:\\ 0 - Phase Register 0.\\ 1 - Phase Register 1. | 
 +**freqRegNo=** | Select ​the frequency register ​to be used. Accepted values:\\ Register number:​\\ ​- Frequency Register 0.\\ 1 - Frequency Register 1. | 
 +| **freqRegNo?​** | Displays ​the selected frequency register. | 
 +**phaseRegNo=** | Select ​the phase register ​to be used. Accepted values:\\ Register number:\\ 0 - Phase Register 0.\\ - Phase Register 1. | 
 +**phaseRegNo?​** | Displays ​the selected phase register. | 
 +| **sleepMode=** | Select one sleep mode. Accepted values:\\ Sleep mode:\\ 0 - No power-down.(default)\\ 1 - DAC powered down.\\ ​- Internal clock disabled. \\ 3 - DAC powered down and Internal clock disabled. | 
 +**sleepMode?​** | Displays ​the selected sleep mode. | 
 + 
  
-**Section D** is used to select ​the sleep mode of the circuit.+Commands can be executed using a serial terminal connected ​to the UART peripheral ​of Xilinx KC705 FPGA.
  
-**Section E** is used to activate and control the Frequency Sweep function+The following image shows a generic list of commands in a serial terminal connected ​to Xilinx KC705 FPGA's UART peripheral
-  * //**Sweep ON / Sweep OFF**// – Turn ON / OFF the sweep function. +{{ :​resources:​fpga:​xilinx:​interposer:​Terminal_KC705.jpg? }}
-  * //**Start / Stop**// – Start / Stop the sweep function. +
-  * //**Start Frequency**//​ – Value of the start frequency. +
-  * //**Stop Frequency**//​ – Value of the stop frequency. +
-  * //**Step Frequency**//​ – Value of the increment size. +
-  * //​**Delay**//​ – Value of the delay between each frequency increment.+
  
-===== Troubleshooting ​=====+===== Software Project Setup ===== 
 +{{page>​import_workspace}}
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: 
-  * Check that the evaluation board is powered as instructed in the board'​s user guide. 
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//​**. 
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. 
  
 ====== More information ====== ====== More information ======
   * [[resources:​tools-software:​linux-drivers:​iio-dds:​ad9834|AD9837 IIO Direct Digital Synthesis Linux Driver]]   * [[resources:​tools-software:​linux-drivers:​iio-dds:​ad9834|AD9837 IIO Direct Digital Synthesis Linux Driver]]
 {{page>​ez_common}} {{page>​ez_common}}
resources/fpga/xilinx/interposer/ad9837.txt · Last modified: 21 Oct 2013 15:22 by LucianS