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resources:fpga:xilinx:interposer:ad9837 [28 Sep 2012 13:39] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina | resources:fpga:xilinx:interposer:ad9837 [21 Oct 2013 15:22] – changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact Lucian Sin | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
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* [[adi>/ | * [[adi>/ | ||
* [[http:// | * [[http:// | ||
- | * [[http:// | ||
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD9837 reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **AD9837 Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **AD9837 Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | + | ||
- | ===== Demonstration Project User Interface | + | |
- | + | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD9837SDZ** evaluation board. | + | |
- | + | ||
- | {{ : | + | |
- | **Section A** is used to activate | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting | ||
+ | </ | ||
- | **Section B** is used to choose the frequency register, the phase register and the signal from the VOUT output. | + | * Use the FMC-SDP interposer |
- | * **// | + | * Connect |
- | * //F1// – FREQ1 register is used in the phase accumulator. | + | |
- | * //F0// – FREQ0 register is used in the phase accumulator. | + | |
- | * **//Phase control// | + | |
- | * //P1// – PHASE1 register data is added to the output of the phase accumulator. | + | |
- | * //P0// – PHASE0 register data is added to the output of the phase accumulator. | + | |
- | * **//VOUT Output// | + | |
- | * //MSB// – MSB of the DAC at the output. | + | |
- | * //MSB/2// – MSB/2 of the DAC at the output. | + | |
- | * // | + | |
- | * // | + | |
- | **Section C** is used to load values | + | ===== Reference Project Overview ===== |
- | | + | The following commands were implemented in this version of EVAL-AD9837 reference project for Xilinx KC705 FPGA board. |
- | | + | ^ Command ^ Description ^ |
- | | + | | **help?** | Displays all available commands. | |
- | | + | | **output=** | Selects the type of output. Accepted |
+ | | **output?** | Displays | ||
+ | | **loadFreqReg=** | Loads a frequency value in one selected register. Accepted values:\\ Register | ||
+ | | **freqRegVal? | ||
+ | | **loadPhaseReg=** | Loads a phase value in one selected register. Accepted values:\\ Register number:\\ 0 - Phase Register 0.\\ 1 - Phase Register 1.\\ Value:\\ 0 .. 2PI - the phase value in radians. | | ||
+ | | **phaseRegVal? | ||
+ | | **freqRegNo=** | Select | ||
+ | | **freqRegNo? | ||
+ | | **phaseRegNo=** | Select | ||
+ | | **phaseRegNo? | ||
+ | | **sleepMode=** | Select one sleep mode. Accepted values:\\ Sleep mode:\\ 0 - No power-down.(default)\\ 1 - DAC powered down.\\ | ||
+ | | **sleepMode? | ||
+ | |||
- | **Section D** is used to select | + | Commands can be executed using a serial terminal connected |
- | **Section E** is used to activate and control the Frequency Sweep function. | + | The following image shows a generic list of commands in a serial terminal connected |
- | * //**Sweep ON / Sweep OFF**// – Turn ON / OFF the sweep function. | + | {{ : |
- | * //**Start / Stop**// – Start / Stop the sweep function. | + | |
- | * //**Start Frequency**// | + | |
- | * //**Stop Frequency**// | + | |
- | * //**Step Frequency**// | + | |
- | * // | + | |
- | ===== Troubleshooting | + | ===== Software Project Setup ===== |
+ | {{page> | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | ||
- | * Check that the evaluation board is powered as instructed in the board' | ||
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | ||
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | ||
====== More information ====== | ====== More information ====== | ||
* [[resources: | * [[resources: | ||
{{page> | {{page> |