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resources:fpga:xilinx:interposer:ad9834 [28 Sep 2012 13:19] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina | resources:fpga:xilinx:interposer:ad9834 [09 Jan 2021 00:49] (current) – user interwiki links Robin Getz | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
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* [[adi> | * [[adi> | ||
* [[adi>/ | * [[adi>/ | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
- | * [[http:// | + | |
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Hardware ===== | ===== Required Hardware ===== | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
* FMC-SDP adapter board | * FMC-SDP adapter board | ||
* **EVAL-AD9834** evaluation board | * **EVAL-AD9834** evaluation board | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD9834 reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **AD9834 Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **AD9834 Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | + | ||
- | ===== Demonstration Project User Interface | + | |
- | + | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD9834SDZ** evaluation board. | + | |
- | + | ||
- | {{ : | + | |
- | + | ||
- | **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **// | + | |
- | + | ||
- | **Section B** is used to set or clear the bits and pins which affect the signal from the IOUT output. | + | |
- | + | ||
- | Programming Method: | + | |
- | + | ||
- | * HW – selects the control pins to implement the register selection, reset, and DAC power-down functions. | + | |
- | * SW – selects the control bits to implement the register selection, reset, and DAC power-down functions. | + | |
- | + | ||
- | Frequency control: | + | |
- | + | ||
- | * F1 – FREQ1 register is used in the phase accumulator. | + | |
- | * F0 – FREQ0 register is used in the phase accumulator. | + | |
- | + | ||
- | Phase control: | + | |
- | + | ||
- | * P1 – PHASE1 register data is added to the output of the phase accumulator. | + | |
- | * P0 – PHASE0 register data is added to the output of the phase accumulator. | + | |
- | + | ||
- | IOUT Output: | + | |
- | + | ||
- | * Ramp – Triangle signal at the output. | + | |
- | * Sin – Sinusoidal signal at the output. | + | |
- | + | ||
- | HW Pins: | + | |
- | + | ||
- | * F1 / F0 – This pin controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. | + | |
- | * P1 / P0 – This pin controls which phase register, PHASE0 or PHASE1, is added to the phase accumulator output. | + | |
- | + | ||
- | Sleep: When this pin is high, the DAC is powered down. | + | |
- | + | ||
- | Reset: This pin resets the appropriate internal registers to 0. | + | |
- | + | ||
- | **Section C** is used to load values in the frequency and phase registers. | + | |
- | A frequency value is set using the corresponding dial and slider controls. | + | |
- | + | ||
- | * put the dial to position 0 and move the slider to 4; | + | |
- | * put the dial to position 1 and move the slider to 3; | + | |
- | * put the dial to position 2 and move the slider to 2; | + | |
- | * put the dial to position 3 and move the slider to 1. | + | |
- | + | ||
- | **Section D** is used to set or clear the bits which affect the signal from the SIGN BIT OUT output. | + | |
- | + | ||
- | Sign Bit Output Options: | + | |
- | + | ||
- | * Enable / Disable – enables / disables the SIGN BIT OUT pin. | + | |
- | * Comparator / DAC – connects the on-board comparator / the MSB of the DAC to the SIGN BIT OUT pin. | + | |
- | * MSB / MSB/2 – Outputs MSB / MSB/2 of the DAC to the SIGN BIT OUT pin. | + | |
- | + | ||
- | **Section E** is used to select the sleep mode of the circuit. | + | |
- | + | ||
- | **Section F** is used to activate and control the Frequency Sweep function. | + | |
- | + | ||
- | Sweep ON / Sweep OFF: Turn ON / OFF the sweep function. | + | |
- | + | ||
- | Start / Stop: Start / Stop the sweep function. | + | |
- | Start Frequency: Value of the start frequency. | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage | ||
+ | </ | ||
- | Stop Frequency: Value of the stop frequency. | + | * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. |
+ | * Connect the JTAG and UART cables to the KC705 and power up the FPGA board. | ||
- | Step Frequency: Value of the increment size. | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented in this version of EVAL-AD9834 reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **output=** | Selects the type of output. Accepted values:\\ 0 - Sinusoid.(default)\\ 1 - Triangle. | | ||
+ | | **output?** | Displays the type of output. | | ||
+ | | **loadFreqReg=** | Loads a frequency value in one selected register. Accepted values:\\ Register number:\\ 0 - Frequency | ||
+ | | **freqRegVal? | ||
+ | | **loadPhaseReg=** | Loads a phase value in one selected register. Accepted values:\\ Register number:\\ 0 - Phase Register 0.\\ 1 - Phase Register 1.\\ Value:\\ 0 .. 2PI - the phase value in radians. | | ||
+ | | **phaseRegVal? | ||
+ | | **freqRegNo=** | Select the frequency register to be used. Accepted values:\\ Register number:\\ 0 - Frequency Register 0.\\ 1 - Frequency Register 1. | | ||
+ | | **freqRegNo? | ||
+ | | **phaseRegNo=** | Select the phase register to be used. Accepted values:\\ Register number:\\ 0 - Phase Register 0.\\ 1 - Phase Register 1. | | ||
+ | | **phaseRegNo? | ||
+ | | **sleepMode=** | Select one sleep mode. Accepted values:\\ Sleep mode:\\ Soft method:\\ 0 - No power-down.(default)\\ 1 - DAC powered down. \\ 2 - Internal clock disabled. \\ 3 - DAC powered down and Internal clock disabled. \\ Hard method: \\ 0 - No power-down.(default)\\ 1 - DAC powered down. | | ||
+ | | **sleepMode? | ||
+ | | **program=** | Sets the programming method. Accepted values:\\ Method:\\ 0 - Soft programming method.(default)\\ 1 - Hard programming method. | | ||
+ | | **program? | ||
+ | | **logicOut=** | Sets the logic output type. Accepted values:\\ Logic output type:\\ 0 - High impedance.(default)\\ 1 - DAC data MSB/2.\\ 2 - DAC data MSB.\\ 3 - Comparator. | | ||
+ | | **logicOut? | ||
+ | |||
- | Delay: Value of the delay between each frequency increment. | + | Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. |
- | ===== Troubleshooting ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | ===== Software Project Setup ===== |
- | * Check that the evaluation board is powered as instructed in the board' | + | {{page> |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
* [[resources: | * [[resources: | ||
{{page> | {{page> |