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resources:fpga:xilinx:interposer:ad9739a [21 Jun 2012 15:57] – changed title to be more meaningful. rejeesh kuttyresources:fpga:xilinx:interposer:ad9739a [20 Dec 2023 11:50] (current) – Add obsolesce notice. Stefan-Robert Raus
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 ====== AD9739A Evaluation Board, DAC-FMC Interposer & Xilinx Reference Design ====== ====== AD9739A Evaluation Board, DAC-FMC Interposer & Xilinx Reference Design ======
    
 +<note warning>**NOTE:**\\
 +Support for the eval-ad9739a is discontinued  starting with 2022_R2 Kuiper Linux release and it will not be supported in future releases. Last release in which pre-build files can be found is 2021_r2. Check this [[:resources:tools-software:linux-software:adi-kuiper_images:release_notes|link]] to see all Kuiper releases.
 +</note>
 +
 ===== Introduction ===== ===== Introduction =====
  
 The [[adi>AD9739A]] is a 14-bit, 2.5GSPS high performance RF digital-to-analog converter (DAC) capable of synthesizing wideband signals from DC up to 3 GHz. This reference design includes a DDS generator that drives both ports of the device. The programming is done via the USB-SPI interface. The [[adi>AD9739A]] is a 14-bit, 2.5GSPS high performance RF digital-to-analog converter (DAC) capable of synthesizing wideband signals from DC up to 3 GHz. This reference design includes a DDS generator that drives both ports of the device. The programming is done via the USB-SPI interface.
  
-**HW Platform(s):** [[http://www.xilinx.com/ml605|Virtex-6 ML605 (Xilinx)]] or [[http://www.xilinx.com/kc705|Kintex-7 KC705 (Xilinx)]] or [[http://www.xilinx.com/vc707|Virtex-7 Vc707 (Xilinx)]] and [[http://www.analog.com/en/digital-to-analog-converters/da-converters/ad9739a/products/EVAL-AD9739A/eb.html|AD9739A Evaluation Board (ADI)]], [[http://www.analog.com/en/digital-to-analog-converters/da-converters/ad-dac-fmc/products/product.html|DAC FMC Interposer Board (ADI)]] \\ +===== Supported Devices ===== 
-**System:** Microblaze, AXI, UART+ 
 +  * [[adi>en/digital-to-analog-converters/da-converters/ad9739a/products/EVAL-AD9739A/eb.html|AD9739A Evaluation Board]] 
 +  * [[adi>en/evaluation/ad-dac-fmc/eb.html|DAC FMC Interposer Board]] 
 + 
 + 
 +===== Supported Carriers ===== 
 + 
 +  * [[xilinx>ML605]]  
 +  * [[xilinx>KC705]]  
 +  * [[xilinx>VC707]]  
 + 
  
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
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   * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).   * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
-  * ADI DPG DAC Software Suite [[http://www.analog.com/en/digital-to-analog-converters/da-converters/products/evaluation-boardstools/CU_eb_DPG_high_speed_DAC_eval_platform/resources/fca.html|available here]].+  * ADI DPG DAC Software Suite [[/resources/eval/dpg/dacsoftwaresuite|available here]].
  
 ==== Bit file ==== ==== Bit file ====
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 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
  
-<note tip>If you are not familiar with ML605 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards/ml605/reference_designs.htm]] for details. 
-</note> 
  
 To begin make the following connections (see image below): To begin make the following connections (see image below):
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 ===== Downloads ===== ===== Downloads =====
  
-{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz.tar.gz|ML605 Reference Design Source Code}}\\ +FPGA Referece Designs: 
-{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_kc705.tar.gz|KC705 Reference Design Source Code}}\\ +<WRAP round download 80%> 
-{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_vc707.tar.gz|VC707 Reference Design Source Code}}\\ +  * **ML605 ** {{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_edk_14_4_2013_03_08.tar.gz}} 
 +  * **KC705 ** {{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_kc705_edk_14_4_2013_03_08.tar.gz}} 
 +  * **VC707 ** {{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_vc707_edk_14_4_2013_03_08.tar.gz}} 
 +</WRAP>
  
-===== Notes =====+Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
  
-The following two files are removed from the tar file.+<WRAP round help 80%> 
 +  * Questions? [[ez>community/fpga|Ask Help & Support]]. 
 +</WRAP>
  
-  * pcores/cf_ad9739a_core_v1_00_a/netlist/cf_ddsx.ngc 
-  * pcores/cf_ad9739a_core_v1_00_a/hdl/verilog/cf_ddsx.v 
  
-To use the reference design as it is, re-generate the Xilinx DDS core for a single sine output (16bit) in full range mode. 
  
 ===== Tar file contents ===== ===== Tar file contents =====
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
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 ===== More information ===== ===== More information =====
  
-  * [[http://www.vita.com/fmc.html|VITA's FMC info]]+  * [[http://www.vita.com/fmc|VITA's FMC info]]
   * [[ez>community/fpga|Ask questions about the FPGA reference design]]   * [[ez>community/fpga|Ask questions about the FPGA reference design]]
  
  
  
resources/fpga/xilinx/interposer/ad9739a.1340287073.txt.gz · Last modified: 21 Jun 2012 15:57 by rejeesh kutty

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