Differences
This shows you the differences between two versions of the page.
| Next revisionBoth sides next revision |
| resources:fpga:xilinx:interposer:ad9683 [08 May 2013 21:16] – created rejeesh kutty | resources:fpga:xilinx:interposer:ad9683 [22 Feb 2017 19:42] – Canonical spelling of JESD204B Lars-Peter Clausen |
|---|
| ===== Using the reference design ===== | ===== Using the reference design ===== |
| |
| The reference design is built on a microblaze based system parameterized for linux. The reference design consists of two pcores. The JESD core consists of the GTX units and the Xilinx JESD 204 IP core. The AD9683 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface. The ADC interface captures and buffers data from the JESD core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. The JESD core and AD9683 core has an AXI lite interface that allows control and monitoring of the capture process. | The reference design is built on a microblaze based system parameterized for linux. The reference design consists of two pcores. The JESD204B core consists of the GTX units and the Xilinx JESD204B IP core. The AD9683 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface. The ADC interface captures and buffers data from the JESD204B core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. The JESD204B core and AD9683 core has an AXI lite interface that allows control and monitoring of the capture process. |
| |
| ==== Registers ==== | ==== Registers ==== |
