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resources:fpga:xilinx:interposer:ad9683 [22 Feb 2017 19:42] Lars-Peter Clausen Canonical spelling of JESD204B |
resources:fpga:xilinx:interposer:ad9683 [28 Jan 2021 19:14] Robin Getz update arrow links after their web site update |
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| ===== Supported Devices ===== | ===== Supported Devices ===== | ||
| - | * [[http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9683/products/product.html#product-evaluationkits| AD9683 Evaluation Board]] | + | * [[adi>en/analog-to-digital-converters/ad-converters/ad9683/products/product.html#product-evaluationkits| AD9683 Evaluation Board]] |
| - | * [[http://www.analog.com/en/evaluation/eval-adc-fmc-int/eb.html| High speed ADC FMC interposer]] | + | * [[adi>en/evaluation/eval-adc-fmc-int/eb.html| High speed ADC FMC interposer]] |
| ===== Supported Carriers ===== | ===== Supported Carriers ===== | ||
| - | * [[xilinx> ZC706]] | + | * [[xilinx>ZC706]] |
| ===== Quick Start Guide ===== | ===== Quick Start Guide ===== | ||
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| </WRAP> | </WRAP> | ||
| - | Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details. | + | Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details. |
| <WRAP round help 80%> | <WRAP round help 80%> | ||
| - | * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]]. | + | * Questions? [[ez>fpga|Ask Help & Support]]. |
| </WRAP> | </WRAP> | ||
| ===== Tar file contents ===== | ===== Tar file contents ===== | ||
| - | The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details. | + | The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details. |
| | license.txt | ADI license & copyright information. | | | license.txt | ADI license & copyright information. | | ||
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| ===== More information ===== | ===== More information ===== | ||
| - | * [[http://www.vita.com/fmc.html|VITA's FMC info]] | + | * [[http://www.vita.com/fmc|VITA's FMC info]] |
| * [[ez>community/fpga|Ask questions about the FPGA reference design]] | * [[ez>community/fpga|Ask questions about the FPGA reference design]] | ||
resources/fpga/xilinx/interposer/ad9683.txt · Last modified: 28 Jan 2021 19:14 by Robin Getz