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resources:fpga:xilinx:interposer:ad9649 [12 Jun 2017 15:02] – Lars-Peter Clausenresources:fpga:xilinx:interposer:ad9649 [28 Jan 2021 19:13] (current) – update arrow links after their web site update Robin Getz
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 ===== Supported Devices ===== ===== Supported Devices =====
  
-  * [[http://www.analog.com/en/evaluation/eval-ad9649/eb.html| AD9649-Evaluation Board]] +  * [[adi>en/evaluation/eval-ad9649/eb.html| AD9649-Evaluation Board]] 
-  * [[http://www.analog.com/en/evaluation/eval-adc-fmc-int/eb.html| High Speed ADC FMC Interposer]]+  * [[adi>en/evaluation/eval-adc-fmc-int/eb.html| High Speed ADC FMC Interposer]]
  
 ===== Supported Carriers ===== ===== Supported Carriers =====
  
-  * [[xilinx> KC705]] +  * [[xilinx>KC705]] 
  
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
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   * Connect power to KC705 and the AD9649 evaluation boards.   * Connect power to KC705 and the AD9649 evaluation boards.
   * Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on KC705.   * Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on KC705.
-  * Follow the [[http://wiki.analog.com/resources/eval/ad9266-80ebz_ad9649-80ebz_ad9629-80ebz_ad9609-80ebz|AD9649 evaluation board setup]] instructions.+  * Follow the [[/resources/eval/ad9266-80ebz_ad9649-80ebz_ad9629-80ebz_ad9609-80ebz|AD9649 evaluation board setup]] instructions.
  
 After the hardware setup, turn the power on to the KC705 and the AD9649 evaluation boards. After the hardware setup, turn the power on to the KC705 and the AD9649 evaluation boards.
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 </WRAP> </WRAP>
  
-Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.+Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
  
 <WRAP round help 80%> <WRAP round help 80%>
-  * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]].+  * Questions? [[ez>fpga|Ask Help & Support]].
 </WRAP> </WRAP>
  
 ===== Tar file contents ===== ===== Tar file contents =====
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
resources/fpga/xilinx/interposer/ad9649.1497272566.txt.gz · Last modified: 12 Jun 2017 15:02 by Lars-Peter Clausen

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