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resources:fpga:xilinx:interposer:ad9467 [18 Nov 2019 16:10] – Update block diagram Stanca-Florina Popresources:fpga:xilinx:interposer:ad9467 [25 Apr 2023 15:34] (current) – Modified the wrong page, so revert changes and add obsolete tag Iulia Moldovan
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 ====== AD9467 Evaluation Board, ADC-FMC Interposer & Xilinx Reference Design ====== ====== AD9467 Evaluation Board, ADC-FMC Interposer & Xilinx Reference Design ======
- + 
 +<note important>This design is **not supported anymore**, thus this wiki page is **kept for legacy purposes only**. The similar design **with an FMC connector is still supported** and can be found here **[[:resources:fpga:xilinx:fmc:ad9467 | AD9467 Native FMC Card / Xilinx Reference Design]]**</note> 
 ===== Introduction ===== ===== Introduction =====
  
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 ===== Supported Devices ===== ===== Supported Devices =====
  
-  * [[http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9467.html#eb-overview|AD9467 Evaluation Board]] +  * [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9467.html#eb-overview|AD9467 Evaluation Board]] 
-  * [[http://www.analog.com/en/evaluation/eval-adc-fmc-int/eb.html | ADC-FMC Interposer A]]+  * [[adi>en/evaluation/eval-adc-fmc-int/eb.html | ADC-FMC Interposer A]]
  
 ===== Supported Carriers ===== ===== Supported Carriers =====
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 </WRAP> </WRAP>
  
-Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.+Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
  
 <WRAP round help 80%> <WRAP round help 80%>
-  * Questions? [[https://ez.analog.com/community/fpga|Ask Help & Support]].+  * Questions? [[ez>community/fpga|Ask Help & Support]].
 </WRAP> </WRAP>
  
 ===== Tar file contents ===== ===== Tar file contents =====
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
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-===== More information ===== +===== Support =====
- +
-  * [[http://www.vita.com/|VITA's FMC info]] +
-  * [[ez>community/fpga|Ask questions about the FPGA reference design]] +
  
 +**As this design is obsolete, we do not fully support it anymore**. Analog Devices will provide **limited** online support for anyone using the reference design with Analog Devices components via the [[ez>community/fpga | EngineerZone FPGA reference designs]] forum.
  
 +It should be noted, that the older the tools' versions and release branches are, the lower the chances to receive support from ADI engineers.
resources/fpga/xilinx/interposer/ad9467.1574089824.txt.gz · Last modified: 18 Nov 2019 16:10 by Stanca-Florina Pop

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