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resources:fpga:xilinx:interposer:ad9467 [14 Jun 2012 19:49] – 14.1 updates rejeesh kuttyresources:fpga:xilinx:interposer:ad9467 [25 Apr 2023 15:34] (current) – Modified the wrong page, so revert changes and add obsolete tag Iulia Moldovan
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-====== AD9467 FMC Interposer & Evaluation Board / Xilinx Reference Design ====== +====== AD9467 Evaluation Board, ADC-FMC Interposer & Xilinx Reference Design ====== 
- + 
 +<note important>This design is **not supported anymore**, thus this wiki page is **kept for legacy purposes only**. The similar design **with an FMC connector is still supported** and can be found here **[[:resources:fpga:xilinx:fmc:ad9467 | AD9467 Native FMC Card / Xilinx Reference Design]]**</note> 
 ===== Introduction ===== ===== Introduction =====
  
-The [[adi>AD9467]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250MSPS. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring it's internal registers via SPI. It also allows programming the [[adi>AD9517-4]] clock chip as an alternative clock source on the board. The board also provides other options to drive the clock to the ADC.+The [[adi>AD9467]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250MSPS. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring its internal registers via SPI. It also allows programming the [[adi>AD9517-4]] clock chip as an alternative clock source on the board. The board also provides other options to drive the clock to the ADC. 
 + 
 +===== Supported Devices ===== 
 + 
 +  * [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9467.html#eb-overview|AD9467 Evaluation Board]] 
 +  * [[adi>en/evaluation/eval-adc-fmc-int/eb.html | ADC-FMC Interposer A]] 
 + 
 +===== Supported Carriers ===== 
 + 
 +  * [[xilinx>ML605]]  
 +  * [[xilinx>KC705]]  
 +  * [[xilinx>VC707]] 
  
-**HW Platform(s):** [[http://www.xilinx.com/products/boards-and-kits/EK-V6-ML605-G.htm|Virtex-6 ML605 (Xilinx)]], [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm|Kintex-7 KC705 (Xilinx)]] or [[http://www.xilinx.com/products/boards-and-kits/EK-V7-VC707-G.htm|Virtex-7 VC707 (Xilinx)]] [[http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9467/products/EVAL-AD9467/eb.html|AD9467 Evaluation Board (ADI)]],  ADC FMC Interposer Board (ADI) \\ 
-**System:** Microblaze, AXI, UART 
  
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
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 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
- 
-<note tip>If you are not familiar with ML605 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards/ml605/reference_designs.htm]] for details. 
-</note> 
  
 To begin make the following connections (see image below): To begin make the following connections (see image below):
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 The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below. The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.
  
-{{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_bd.jpg?400|block diagram}}+=== Xilinx block diagram === 
 +{{:resources:fpga:xilinx:fmc:ad9467_ebz:ad9467_fmc.svg?500|Xilinx HDL Block Diagram}} 
 + 
 +=== AD9467 FMC Card block diagram === 
 +{{:resources:fpga:xilinx:fmc:ad9467_ebz:ad9467_fmc_card.svg?400|Xilinx HDL Block Diagram}}
  
 The reference design consists of three functional modules, a LVDS interface, a PN9/PN23/PAT monitor and a DMA interface.  The reference design consists of three functional modules, a LVDS interface, a PN9/PN23/PAT monitor and a DMA interface. 
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 ===== Downloads ===== ===== Downloads =====
  
-{{:resources:fpga:xilinx:interposer:cf_ad9467_ebz.tar.gz|ML605 Reference Design Source Code}}\\ +FPGA Referece Designs: 
-{{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_kc705.tar.gz|KC705 Reference Design Source Code}}\\ +<WRAP round download 80%> 
-{{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_vc707.tar.gz|VC707 Reference Design Source Code}}\\+  * **ML605 ** {{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_edk_14_4_2013_03_08.tar.gz}} 
 +  * **KC705 ** {{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_kc705_edk_14_4_2013_03_08.tar.gz}} 
 +  * **VC707 ** {{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_vc707_edk_14_4_2013_03_08.tar.gz}} 
 +</WRAP>
  
 +Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
 +
 +<WRAP round help 80%>
 +  * Questions? [[ez>community/fpga|Ask Help & Support]].
 +</WRAP>
  
 ===== Tar file contents ===== ===== Tar file contents =====
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
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-===== More information ===== +===== Support =====
- +
-  * [[http://www.vita.com/fmc.html|VITA's FMC info]] +
-  * [[ez>community/fpga|Ask questions about the FPGA reference design]] +
  
 +**As this design is obsolete, we do not fully support it anymore**. Analog Devices will provide **limited** online support for anyone using the reference design with Analog Devices components via the [[ez>community/fpga | EngineerZone FPGA reference designs]] forum.
  
 +It should be noted, that the older the tools' versions and release branches are, the lower the chances to receive support from ADI engineers.
resources/fpga/xilinx/interposer/ad9467.1339696198.txt.gz · Last modified: 14 Jun 2012 19:49 by rejeesh kutty

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