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AD9467 FMC Interposer & Evaluation Board / Xilinx ML-605 Reference Design

Introduction

The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250MSPS. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring it's internal registers via SPI. It also allows programming the AD9517-4 clock chip as an alternative clock source on the board. The board also provides other options to drive the clock to the ADC.

HW Platform(s): Virtex-6 ML605 (Xilinx), AD9467 Evaluation Board (ADI), ADC FMC Interposer Board (ADI)
System: Microblaze, AXI, UART

Quick Start Guide

The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).

Required Hardware

  • ML605 board
  • AD9467-2x0EBZ board & Power supply
  • ADC FMC interposer board
  • Signal/Clock generator (200MHz or 250MHz)

Required Software

  • Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
  • A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.

Bit file

  • Download the gzip file and extract the sw/cf_ad9467_ebz.bit file.

Board Modifications

If you have a Rev. A version of the FMC interposer board, please do the following modifications on the board.

  • Populate R209 (0ohm) and make sure R211 is NOT populated.
  • Insert (cut the traces) 33ohm resistors on U201 (UG3308) Y ports (pins 11 through 17).
  • Make sure that R201 through R207 are NOT populated.

If you have a Rev. A version of the AD9467 evaluation board, please do the following modifications on the board.

  • Remove R309 on pin 14 of AD9517 (U300).
  • Remove R600 on pin 3 of NC7WZ16P (U601).
  • Remove R601 on pin 1 of NC7WZ16P (U601).
  • Remove R602 on pin 1 of NC7WZ07P (U600).

Running Demo (SDK) Program

If you are not familiar with ML605 and/or Xilix tools, please visit
http://www.xilinx.com/products/boards/ml605/reference_designs.htm for details.

To begin make the following connections (see image below):

  • Connect the AD9467-2x0EBZ board to the FMC Interposer board.
  • Connect the interposer board to the FMC-HPC connector of ML605 board.
  • Connect power to ML605 and the AD9467-2x0EBZ boards.
  • Connect two USB cables from the PC to the JTAG and UART USB connectors on ML605.
  • Connect an external clock source to AD9467-2x0EBZ board's J201 SMA connector.

If you have AD9467-200EBZ board setup the clock source to be 200MHz, if AD9467-250EBZ set up the clock source to be 250MHz. This quick start bit file configures the AD9467 for all test modes and verifies the captured data accordingly. After the hardware setup, turn the power on to the ML605 and the AD9467-2x0EBZ boards.

Hardware setup

Start IMPACT, and initialze the JTAG chain. The program should recognize the Virtex 6 device (see screenshot below). Start a UART terminal (set to 57600 baud rate) and then program the device.

IMPACT

If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9467 and AD9517, the program checks data capture on various test modes. Please note that AD9517 is powered down by default but is still accessable via SPI.

Terminal

Using the reference design

Functional description

The reference design consists of three functional modules, a capture interface, a DMA interface and a SPI interface.

The capture interface uses the IDDR to register ADC data. It is then transferred to the DMA module. The DMA module interfaces to the Xilinx AXI-DMA engine and stores a programmable number of samples on the external DDR-DRAM on ML605.

The SPI interface allows programming the AD9517 and/or AD9467. The provided SDK software shows the access methods for SPI reads and writes on both the devices.

Registers

QW Address1 Bits Default Name Description
0x00 31 0x10061 version 32'h00_01_00_61
0x01 25 0 SPI start SPI access start (a 0x0 to 0x1 initiates start).
24 0 SPI select SPI device select AD9517 (0x1) or AD9467 (0x0).
23:8 0 SPI address SPI address.
7 0 SPI write data SPI write data.
0x02 8 0 SPI status SPI idle (0x1) or busy (0x0) status.
7:0 0 SPI read data SPI read data.
0x03 16 0 ADC capture start ADC capture start (a 0x0 to 0x1 initiates start).
15:0 0 ADC capture count ADC capture count (total count - 1).
0x04 2 0 DMA underflow DMA underflow (W1C).
1 0 DMA overflow DMA overflow (W1C).
0 0 DMA status DMA idle (0x0) or busy (0x1) status.
0x05 0 0 ADC OR ADC OR (W1C).
0x06 31:0 0 ADC sample ADC captured sample (debug purposes only).
1. For AXI-Lite byte addresses, multiply by 4.
2. W1C: write 1 to clear the bit.

Clock Selection

There are several clock paths available on the evaluation board.

Downloads

Tar file contents

The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.

license.txt ADI license & copyright information.
system.bsb BSB wizard file (optional).
system.mhs MHS file.
system.xmp XMP file (use this file to build the reference design).
data/ UCF file and/or DDR MIG project files.
docs/ Documentation files (Please note that this wiki page is the documentation for the reference design).
ise/ ISE project file(s) (for stand alone build) and/or simulation (optional).
pcores/ Reference design core file(s) (Xilinx EDK).
scripts/ Individual scripts for platgen, xst, xflow etc. for command line run.
sw/ Software (Xilinx SDK) & bit file(s).
tb/ Test bench source file(s) (optional).

More information

resources/fpga/xilinx/interposer/ad9467.1323458688.txt.gz · Last modified: 09 Dec 2011 20:24 by rejeesh kutty