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resources:fpga:xilinx:interposer:ad9467 [25 Apr 2023 10:56] – Separate obsolete section Iulia Moldovan | resources:fpga:xilinx:interposer:ad9467 [25 Apr 2023 15:34] (current) – Modified the wrong page, so revert changes and add obsolete tag Iulia Moldovan | ||
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====== AD9467 Evaluation Board, ADC-FMC Interposer & Xilinx Reference Design ====== | ====== AD9467 Evaluation Board, ADC-FMC Interposer & Xilinx Reference Design ====== | ||
- | + | ||
- | This wiki page contains sections with obsolete information, | + | <note important> |
===== Introduction ===== | ===== Introduction ===== | ||
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The [[adi> | The [[adi> | ||
- | ===== Supported | + | ===== Supported |
* [[adi> | * [[adi> | ||
* [[adi> | * [[adi> | ||
- | ===== Supported | + | ===== Supported |
- | + | ||
- | * [[xilinx> | + | |
- | * [[https:// | + | |
- | * [[xilinx> | + | |
- | * [[xilinx> | + | |
- | + | ||
- | ===== Quick start guide ===== | + | |
- | + | ||
- | ==== Required hardware ==== | + | |
- | + | ||
- | ==== Required software ==== | + | |
- | + | ||
- | * ZedBoard or KC705 board | + | |
- | * AD9467-FMC-250EBZ | + | |
- | * Signal/ | + | |
- | * Signal generator (analog input, for data capture) | + | |
- | * UART terminal (Tera Term/ | + | |
- | + | ||
- | ==== Hardware modifications | + | |
- | ===== Obsolete quick start guide ===== | + | * [[xilinx> |
+ | * [[xilinx> | ||
+ | * [[xilinx> | ||
- | This quick start guide is kept for legacy purposes only, and the designs on carriers ML605 and VC707 are no longer supported. | ||
- | ++++ Click to expand Obsolete | + | ===== Quick Start Guide ===== |
The reference design has been tested with ML605, KC705 and VC707. The notes below refer to ML605, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). | The reference design has been tested with ML605, KC705 and VC707. The notes below refer to ML605, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). | ||
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==== Required Hardware ==== | ==== Required Hardware ==== | ||
- | * ML605, KC705 or VC707 board | + | * ML605, KC705 or VC707 board |
* AD9467-2x0EBZ board & Power supply | * AD9467-2x0EBZ board & Power supply | ||
* ADC FMC interposer board | * ADC FMC interposer board | ||
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* Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | ||
- | * UART terminal (Tera Term/ | + | * A UART terminal (Tera Term/ |
==== Bit file ==== | ==== Bit file ==== | ||
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Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/ | Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/ | ||
+ | <WRAP round help 80%> | ||
+ | * Questions? [[ez> | ||
+ | </ | ||
===== Tar file contents ===== | ===== Tar file contents ===== | ||
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| cf_lib/ | | cf_lib/ | ||
- | ++++ | ||
- | ===== More information | + | ===== Support |
+ | |||
+ | **As this design is obsolete, we do not fully support it anymore**. Analog Devices will provide **limited** online support for anyone using the reference design with Analog Devices components via the [[ez> | ||
- | * [[http:// | + | It should be noted, that the older the tools' |
- | * [[ez> | + |