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| resources:fpga:xilinx:interposer:ad9279 [20 Nov 2012 10:33] – [Introduction] use short link Lars-Peter Clausen | resources:fpga:xilinx:interposer:ad9279 [26 Mar 2013 14:42] – [Downloads] rejeesh kutty |
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| The [[adi>AD9279]] is an eight channel variable gain amplifier (VGA) with a low noise preamplifier (LNA), an antialiasing filter (AAF), an analog-to-digital converter (ADC) and an I/Q demodulator with programmable phase rotation. It is a low cost, low power, small size device for applications in medical ultrasound and automotive radar. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring it's internal registers via SPI. The reference design is based on ML605. | The [[adi>AD9279]] is an eight channel variable gain amplifier (VGA) with a low noise preamplifier (LNA), an antialiasing filter (AAF), an analog-to-digital converter (ADC) and an I/Q demodulator with programmable phase rotation. It is a low cost, low power, small size device for applications in medical ultrasound and automotive radar. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring it's internal registers via SPI. The reference design is based on ML605. |
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| **HW Platform:** [[http://www.xilinx.com/ml605|Virtex-6 ML605 (Xilinx)]], [[adi>AD9279-65EBZ|AD9279-65EBZ customer evaluation board (ADI)]] and the ADC FMC Interposer Board (ADI) \\ | ===== Supported Devices ===== |
| **System:** Microblaze, AXI, UART | |
| | * [[adi>AD9279-65EBZ|AD9279-65EBZ customer evaluation board]] |
| | * [[adi>en/evaluation/eval-adc-fmc-int/eb.html| ADC FMC Interposer board]] |
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| | ===== Supported Carriers ===== |
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| | * [[xilinx> ML605]] |
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| ===== Quick Start Guide ===== | ===== Quick Start Guide ===== |
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| ===== Downloads ===== | ===== Downloads ===== |
| | FPGA Referece Designs: |
| | <WRAP round download 80%> |
| | * **ML605 (source files)** {{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_edk_14_4_2013_03_26.tar.gz}} |
| | * **ML605 (bit/sw files)** {{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_sw_14_4_2013_03_26.tar.gz}} |
| | </WRAP> |
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| | Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details. |
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| | <WRAP round help 80%> |
| | * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]]. |
| | </WRAP> |
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| {{:resources:fpga:xilinx:interposer:cf_ad9279_ebz.tar.gz|ML605 Reference Design Source Code}}\\ | |
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| ===== Tar file contents ===== | ===== Tar file contents ===== |
