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resources:fpga:xilinx:interposer:ad9129 [21 Jun 2012 21:19] – created rejeesh kuttyresources:fpga:xilinx:interposer:ad9129 [28 Jan 2021 19:13] (current) – update arrow links after their web site update Robin Getz
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 ===== Introduction ===== ===== Introduction =====
  
-The [[adi>AD9129]] is a 14-bit, high performance digital-to-analog converter (ADC) that provides a sample rate of 2.8GSPS. This reference design includes a DDS generator that drives the device. The programming is done via the USB-SPI interface.+The [[adi>AD9129]] is a 14-bit, high performance digital-to-analog converter (DAC) that provides a sample rate of 2.8GSPS. This reference design includes a DDS generator that drives the device. The programming is done via the USB-SPI interface. 
 + 
 +===== Supported Devices ===== 
 + 
 +  * [[adi>en/digital-to-analog-converters/da-converters/ad9129/products/EVAL-AD9129/eb.html|AD9129 Evaluation Board]] 
 +  * [[adi>en/evaluation/ad-dac-fmc/eb.html|DAC FMC Interposer Board]]  
 + 
 +===== Supported Carriers ===== 
 + 
 +  * [[xilinx>ML605]] 
  
-**HW Platform(s):** [[http://www.xilinx.com/products/boards-and-kits/EK-V6-ML605-G.htm|Virtex-6 ML605 (Xilinx)]], [[http://www.analog.com/en/digital-to-analog-converters/da-converters/ad9129/products/EVAL-AD9129/eb.html|AD9129 Evaluation Board (ADI)]], [[http://www.analog.com/en/evaluation/ad-dac-fmc/eb.html|DAC FMC Interposer Board (ADI)]] \\ 
-**System:** Microblaze, AXI, UART 
  
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
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   * Xilinx ISE 14.1 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).   * Xilinx ISE 14.1 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
-  * ADI DPG DAC Software Suite [[http://www.analog.com/en/digital-to-analog-converters/da-converters/products/evaluation-boardstools/CU_eb_DPG_high_speed_DAC_eval_platform/resources/fca.html|available here]].+  * ADI DPG DAC Software Suite [[/resources/eval/dpg/dacsoftwaresuite|available here]].
  
 ==== Bit file ==== ==== Bit file ====
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 ===== Downloads ===== ===== Downloads =====
  
-{{:resources:fpga:xilinx:interposer:cf_ad9129_ebz.tar.gz|Reference Design Source Code}} +<WRAP round download 80%> 
- +  * **ML605 Source files ** {{:resources:fpga:xilinx:interposer:cf_ad9129_ebz_edk_14_4_2013_03_12.tar.gz}} 
-===== Notes ===== +  * **ML605 SW/Bit files ** {{:resources:fpga:xilinx:interposer:cf_ad9129_ebz_sw_14_4_2013_03_12.tar.gz}} 
- +</WRAP>
-The following two files are missing from the tar file.+
  
-  * netlist/cf_ddsx.ngc +Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
-  * hdl/verilog/cf_ddsx.v+
  
-To use the reference design as it is, re-generate these two files (16bit full-range sine DDS).+<WRAP round help 80%> 
 +  * Questions? [[ez>fpga|Ask Help & Support]]. 
 +</WRAP>
  
 ===== Tar file contents ===== ===== Tar file contents =====
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
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 ===== More information ===== ===== More information =====
  
-  * [[http://www.vita.com/fmc.html|VITA's FMC info]]+  * [[http://www.vita.com/fmc|VITA's FMC info]]
   * [[ez>community/fpga|Ask questions about the FPGA reference design]]   * [[ez>community/fpga|Ask questions about the FPGA reference design]]
  
  
  
resources/fpga/xilinx/interposer/ad9129.1340306359.txt.gz · Last modified: 21 Jun 2012 21:19 by rejeesh kutty

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