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resources:fpga:xilinx:interposer:ad7983 [16 Feb 2012 16:17] – Approved Andrei Cozmaresources:fpga:xilinx:interposer:ad7983 [14 Jan 2021 06:09] (current) – use xilinx> interwiki links Robin Getz
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 {{ :resources:fpga:xilinx:interposer:ad7983.jpg?400 }} {{ :resources:fpga:xilinx:interposer:ad7983.jpg?400 }}
  
-For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: +{{page>common_sdp}}
-  * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)** +
-  * a compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]] +
-  * corresponding PC software +
-The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software.  Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.+
  
 Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7983SDZ** Evaluation Board. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7983SDZ** Evaluation Board.
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   * [[adi>AD7983|AD7983 Product Info]] - pricing, samples, datasheet   * [[adi>AD7983|AD7983 Product Info]] - pricing, samples, datasheet
   * {{:resources:fpga:altera:bemicro:user_guide_eval_10lead_pulsar.pdf|EVAL-AD7980SDZ evaluation board user guide}}   * {{:resources:fpga:altera:bemicro:user_guide_eval_10lead_pulsar.pdf|EVAL-AD7980SDZ evaluation board user guide}}
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Hardware ===== ===== Required Hardware =====
  
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
   * FMC-SDP adapter board   * FMC-SDP adapter board
   * **EVAL-AD7983SDZ** evaluation board   * **EVAL-AD7983SDZ** evaluation board
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 ===== Hardware Setup ===== ===== Hardware Setup =====
  
-<note important>Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.</note>+<WRAP important>Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.</WRAP>
  
   * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.   * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
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   * Start a UART terminal and set the baud rate to 115200 bps.   * Start a UART terminal and set the baud rate to 115200 bps.
  
-At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the ADC run the //data_capture.bat// script located in the //DataCapture// folder from the reference design .zip file. Every time the script is run a new batch of 8192 samples are read from the ADC and saved into the //Acquisition.csv// file located in the same folder as the data capture script. On the UART terminal messages will be displayed to show the status of the program running on the FPGA as shown in the picture below.+At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the ADC run the //data_capture.bat// script located in the //DataCapture// folder from the reference design .zip file. Every time the script is run a new batch of 8192 samples are read from the ADC at the ADC's maximum sampling rate and saved into the //Acquisition.csv// file located in the same folder as the data capture script. On the UART terminal messages will be displayed to show the status of the program running on the FPGA as shown in the picture below.
  
 {{ :resources:fpga:xilinx:interposer:teraterm_adc.png?400 }} {{ :resources:fpga:xilinx:interposer:teraterm_adc.png?400 }}
  
-<note tip>The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore.</note>+<WRAP tip>The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore.</WRAP>
  
 ====== More information ====== ====== More information ======
-  * [[ez>community/fpga|ask questions about the FPGA reference design]] +{{page>ez_common}}
resources/fpga/xilinx/interposer/ad7983.1329405444.txt.gz · Last modified: 16 Feb 2012 16:17 by Andrei Cozma