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resources:fpga:xilinx:interposer:ad7983 [16 Feb 2012 16:17] – Approved Andrei Cozmaresources:fpga:xilinx:interposer:ad7983 [28 Sep 2012 10:41] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina
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 {{ :resources:fpga:xilinx:interposer:ad7983.jpg?400 }} {{ :resources:fpga:xilinx:interposer:ad7983.jpg?400 }}
  
-For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: +{{page>common_sdp}}
-  * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)** +
-  * a compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]] +
-  * corresponding PC software +
-The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software.  Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.+
  
 Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7983SDZ** Evaluation Board. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7983SDZ** Evaluation Board.
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   * Start a UART terminal and set the baud rate to 115200 bps.   * Start a UART terminal and set the baud rate to 115200 bps.
  
-At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the ADC run the //data_capture.bat// script located in the //DataCapture// folder from the reference design .zip file. Every time the script is run a new batch of 8192 samples are read from the ADC and saved into the //Acquisition.csv// file located in the same folder as the data capture script. On the UART terminal messages will be displayed to show the status of the program running on the FPGA as shown in the picture below.+At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the ADC run the //data_capture.bat// script located in the //DataCapture// folder from the reference design .zip file. Every time the script is run a new batch of 8192 samples are read from the ADC at the ADC's maximum sampling rate and saved into the //Acquisition.csv// file located in the same folder as the data capture script. On the UART terminal messages will be displayed to show the status of the program running on the FPGA as shown in the picture below.
  
 {{ :resources:fpga:xilinx:interposer:teraterm_adc.png?400 }} {{ :resources:fpga:xilinx:interposer:teraterm_adc.png?400 }}
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 ====== More information ====== ====== More information ======
-  * [[ez>community/fpga|ask questions about the FPGA reference design]] +{{page>ez_common}}
resources/fpga/xilinx/interposer/ad7983.txt · Last modified: 14 Jan 2021 06:09 by Robin Getz

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