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resources:fpga:xilinx:interposer:ad7657_1 [21 Dec 2012 16:28] – created Alexandru.Tofanresources:fpga:xilinx:interposer:ad7657_1 [14 Jan 2021 06:09] (current) – use xilinx> interwiki links Robin Getz
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   * [[adi>AD7657-1|AD7657-1 Product Info]] - pricing, samples, datasheet   * [[adi>AD7657-1|AD7657-1 Product Info]] - pricing, samples, datasheet
   * {{:resources:fpga:altera:bemicro:user_guide_eval_10lead_pulsar.pdf|EVAL-AD7657-1SDZ evaluation board user guide}}   * {{:resources:fpga:altera:bemicro:user_guide_eval_10lead_pulsar.pdf|EVAL-AD7657-1SDZ evaluation board user guide}}
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Hardware ===== ===== Required Hardware =====
  
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
   * FMC-SDP adapter board   * FMC-SDP adapter board
   * **EVAL-AD7657-1SDZ** evaluation board   * **EVAL-AD7657-1SDZ** evaluation board
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 ===== Hardware Setup ===== ===== Hardware Setup =====
  
-<note important>Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.</note>+<WRAP important>Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.</WRAP>
  
   * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.   * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
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 {{ :resources:fpga:xilinx:interposer:teraterm_adc.png?400 }} {{ :resources:fpga:xilinx:interposer:teraterm_adc.png?400 }}
  
-<note tip>The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore.</note>+<WRAP tip>The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore.</WRAP>
  
 ====== More information ====== ====== More information ======
 {{page>ez_common}} {{page>ez_common}}
resources/fpga/xilinx/interposer/ad7657_1.txt · Last modified: 14 Jan 2021 06:09 by Robin Getz

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