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resources:fpga:xilinx:interposer:ad5780 [28 Sep 2012 11:24]
AdrianC Added common section for describing the evaluation setup and System Demonstration Platform
resources:fpga:xilinx:interposer:ad5780 [30 Sep 2013 15:08] (current)
LucianS [Reference Project Overview]
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>​AD5780|EVAL-AD5780SDZ]]** evaluation board together with the Xilinx KC705 FPGA boardthe Xilinx Embedded Development Kit (EDK) and the [[http://​micrium.com/​page/​products/​tools/​probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5780SDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>​AD5780|EVAL-AD5780SDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5780SDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :​resources:​fpga:​xilinx:​interposer:​img_ad5780.jpg?​400 }} {{ :​resources:​fpga:​xilinx:​interposer:​img_ad5780.jpg?​400 }}
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   * [[adi>/​static/​imported-files/​user_guides/​UG-256.pdf|EVAL-AD5780SDZ evaluation board user guide]]   * [[adi>/​static/​imported-files/​user_guides/​UG-256.pdf|EVAL-AD5780SDZ evaluation board user guide]]
   * [[http://​www.xilinx.com/​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://​www.xilinx.com/​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://​micrium.com/​page/​products/​tools/​probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack)+  * Xilinx ISE 14.6
-  * [[http://micrium.com/​page/​products/​tools/​probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal),​ baud rate 115200. 
 +  * The EVAL-AD5780 reference project for Xilinx KC705 FPGA.
  
 ===== Downloads ===== ===== Downloads =====
- +<WRAP round download 80%> 
-  * {{:resources:​fpga:xilinx:​interposer:​ad5780_evalboard.zip|Reference Design Files}} +\\ 
- +  * **AD5780 Driver:** https://github.com/​analogdevicesinc/​no-OS/​tree/​master/​device_drivers/​AD5791 
-The following table presents a short description the reference design archive contents. +  * **AD5780 Commands:** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/​device_commands/​AD5791 
- +  ​* **Xilinx Boards Common Drivers:** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/​platform_drivers/​Xilinx/​SDP_Common 
-**Folder** **Description** +  * **EDK KC705 Reference ​project:** https://​github.com/​analogdevicesinc/​fpgahdl_xilinx/​tree/​master/​cf_sdp_kc705 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation| +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +</​WRAP>​
-| Software | Contains the source files of the software ​project ​that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. |+
  
 ====== Run the Demonstration Project ====== ====== Run the Demonstration Project ======
  
-{{page>​ucprobe_common}}+===== Hardware setup =====
  
-===== Demonstration Project User Interface =====+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</​WRAP>​
  
-The following figure presents ​the **uC-Probe** interface that can be used for monitoring ​and controlling ​the operation of the **EVAL-AD5780SDZ** evaluation ​board.+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  ​Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-{{ :resources:​fpga:​altera:​bemicro:​ad5780interface.png?700 }}+<WRAP round important 80%> 
 +\\ 
 +To power on the EVAL-AD5780 evaluation board, you need to provide external differential supply voltage to J2 connector(for more information see[[adi>/​static/​imported-files/​user_guides/​UG-256.pdf|EVAL-AD5780SDZ evaluation board user guide]]) and a 5V reference voltage to VREF connector on the evaluation board. VREFN will be connected to AGND (LK8 option=B, LK2 option=B, LK3 option=B, LK4 inserted). 
 +</​WRAP>​
  
-The communication with the board is activated / deactivated by toggling the **//​ON/​OFF//​** switch. The **//​Activity//​** LED turns green when the communication is active. If the **//​ON/​OFF//​** switch is set to **//ON//** and the Activity LED is BLACK it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. 
  
-The value of the AD5780 ​//DAC Register// is changed using the slider located under the **//DAC Register Value (18-bit)//** label. The selected value is displayed in the numeric box located next to the sliderNext to it, the value that is read from the DAC register ​is displayedThe slider will select ​the DAC value as a binery offset valueIn case the coding on the DAC is 2's Complement, ​the value set and the readback ​value will differ.+===== Reference Project Overview ===== 
 +The following commands were implemented in this version ​of EVAL-AD5780 ​reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **reset!** | Resets ​the device. | 
 +**coding=** | Selects the coding style. Accepted values:\\ 0 Two's complement coding.(default)\\ 1 - Offset binary coding. | 
 +**coding?** | Display ​the current coding style. | 
 +| **register=** | Writes ​to the DAC registerAccepted values:\\ 0 .. 262143 - the value written ​to the DAC. | 
 +| **register?​** | Displays last written ​value to the DAC register. ​
 +| **voltage=** | Sets the DAC output voltageAccepted values:\\ -10 .. +10 - desired output voltage in volts. | 
 +| **voltage?​** | Displays ​the output voltage. | 
 +| **output=** | Selects ​the DAC output state. Accepted values:\\ 0 - Normal state.\\ 1 - Clamped via 6KOhm to AGND.(default)\\ ​- Tristate. | 
 +| **output?** | Displays ​the DAC output state. | 
 +| **rbuf=** | Sets/resets the RBUF bit from control register. Accepted values:\\ 0 - RBUF is reset.\\ 1 - RBUF is set.(default) | 
 +| **rbuf?** | Displays ​the value of RBUF bit from control register|
  
-The value of the AD5780 Clearcode Register is changed using the slider located under the **//​Clearcode Register Value (18-bit)//​** label. The selected value is displayed in the numeric box located next to the slider. Next to it, the value that is read from the Clearcode register is displayed. 
  
-The sliders **//​Vref+//​** and **//​Vref-//​** are used to specify ​the reference voltages set on the evaluation board. The default values are +10V and -10V.+Commands can be executed using a serial terminal connected ​to the UART peripheral of Xilinx KC705 FPGA.
  
-The DAC’s output voltage is displayed ​in the numeric box having the label **//Output voltage//**This value is computed based on the Vref+ and Vref- values.+The following image shows a generic list of commands ​in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :​resources:​fpga:​xilinx:​interposer:​Terminal_KC705.jpg? }}
  
-The values of the //Control Register’s//​ bits are indicated by the LEDs situated under the **//Control Register//​** label. When a LED id lit it means that the corresponding bit’s value is 1. Each switch under the LEDs can be used to toggle the corresponding bit in the Control register. +===== Software Project Setup ===== 
- +{{page>​import_workspace}}
-The values of the //Software Control Register’s//​ bits are indicated by the LEDs situated under the **//Status Control Register//​** label. When a LED id lit it means that the corresponding bit’s value is 1. Each switch can be used to toggle the corresponding bit in the Software Control Register. +
- +
-The hardware pins can be controlled by the switches under the label "​Hardware pins". When the switch is active, the corresponding pin will be activated (will be toggled LOW). +
- +
-===== Troubleshooting ​===== +
- +
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +
-  * Check that the evaluation board is powered as instructed in the board'​s user guide. +
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//​**. +
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+
  
 ====== More information ====== ====== More information ======
   * [[resources:​tools-software:​linux-drivers:​iio-dac:​ad5791|AD5780 IIO DAC Linux Driver]]   * [[resources:​tools-software:​linux-drivers:​iio-dac:​ad5791|AD5780 IIO DAC Linux Driver]]
 {{page>​ez_common}} {{page>​ez_common}}
- 
resources/fpga/xilinx/interposer/ad5780.txt · Last modified: 30 Sep 2013 15:08 by LucianS