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AD5755 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design

Supported Devices

Evaluation Boards

Overview

This document presents the steps to setup an environment for using the EVAL-AD5755SDZ evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the Micrium µC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-AD5755SDZ Evaluation Board with the Xilinx KC705 board.

img_ad5755.jpg

For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices System Demonstration Platform (SDP). The SDP consists of a:

The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.

Below is presented a picture of SDP-B Controller Board with the EVAL-AD5755SDZ Evaluation Board.

The AD5755 is a quad, voltage and current output DAC that operates with a power supply range from -26.4 V to +33 V. On-chip dynamic power control minimizes package power dissipation in current mode. This is achieved by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on chip power dissipation. For AD5755-1, each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output.

The EVAL-AD5755SDZ evaluation board is designed to help customers quickly prototype new AD5755 circuits and reduce design time. To power the AD5755SDZ evaluation board supply +/-15V between the AVSS (-15V) and AVDD (+15V) inputs for the analog supply and 5V between PGND(0V) and AVCC(+5V) as DC-to-DC supply voltage.

More information

Getting Started

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

Required Hardware

Required Software

  • Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
  • uC-Probe run-time monitoring tool

Downloads

The following table presents a short description the reference design archive contents.

Folder Description
Bit Contains the KC705 configuration file that can be used to program the system for quick evaluation.
Microblaze Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA.
Software Contains the source files of the software project that will be run by the Microblaze processor.
uCProbeInterface Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory.

Run the Demonstration Project

Hardware Setup

Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.

  • Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
  • Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  • Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Kintex 7 device (see screenshot below).

  • Program the KC705 FPGA using the “Bit/download.bit” file provided in the reference design archive.
  • Power the ADI evaluation board.

At this point everything is set up and it is possible to start the evaluation of the ADI hardware through the controls in the uC-Probe application provided in the reference design.

Configure uC-Probe

Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.

Select uC-Probe options.

  • Click on the uC-Probe icon on the top left portion of the screen.
  • Click on the Options button to open the dialog box.

Set target board communication protocol as RS-232

  • Click on the Communication tab icon on the top left portion of the dialog box
  • Select the RS-232 option.

Setup RS-232 communication settings

  • Select the RS-232 option from the Communication tab.
  • Select the COM port to which the KC705 board is connected.
  • Set the Baud Rate to 115200 bps.

  • Press Apply and OK to exit the options menu.

Load and Run the Demonstration Project

  • Click the Open option from the uC-Probe menu and select the .wsp file from the ucProbeInterface folder provided within the reference design files.
  • Before opening the interface uC-Probe will ask for a symbols file that must be associated with the interface. Select the file ucProbeInterface/ADIEvalBoard.elf to be loaded as a symbol file.
  • Run the demonstration project by pressing the Play button.

  • In some cases it is possible that the uC-Probe interface will not respond to the commands the first time it is ran. In this situation just stop the interface by pressing the Stop button and run it again by pressing the Play button.
  • After starting the uC-Probe interface wait until the status of the connection with the board displayed on the bottom of the screen is set to Connected. It is possible to use the interface only after the status is changed to Connected and the data transfer speed displayed next to the connection status is different than 0.
16 Feb 2012 09:23 · acozma

Demonstration Project User Interface

The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-AD5755SDZ evaluation board.

Section A is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board.

Section B is used to select the DAC channel.

Section C is used to write data into the register selected by the Selection Slider.

Options:

  • Write to DAC data register (individual channel write).
  • Write to gain register (individual channel write).
  • Write to gain register (all DACs).
  • Write to offset register (individual channel write).
  • Write to offset register (all DACs) .
  • Write to clear code register (individual channel write).

Section D is used to read data from the register selected by the Selection Slider.

Options:

  • Read from DAC data register (individual channel read).
  • Read from DAC control register (individual channel read).
  • Read from Gain register (individual channel read).
  • Read from Offset register (individual channel read).
  • Read from Clear Code register (individual channel read).
  • Read from Slew Rate control register (individual channel read).
  • Read from Status register.
  • Read from Main control register.
  • Read from DC-to-DC control register.

Section E is used to write data into the DAC n Control Register.

Options:

  • Internal – Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel.
  • Clear – Clear enable bit.
  • Output – Enables/disables the selected output channel.
  • Rset – Selects an internal or external current sense resistor for the selected DAC channel.
  • DC-DC – Powers the dc-to-dc converter on the selected channel.
  • OVRNG – Enables 20% overrange on voltage output channel only. No current output overrange available.
  • Output Range – Selects the output range to be enabled.

Section F is used to write data into the DC-DC Control Register.

Options:

  • DC-DC Comp – Selects between an internal and external compensation resistor for the dc-to-dc converter.
  • Phase – User programmable dc-to-dc converter phase (between channels).
  • Frequency – DC-to-dc switching frequency.
  • Max Voltage – Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter.

Section G is used to write data into the Main Control Register.

Options:

  • POC – The POC bit determines the state of the voltage output channels during normal operation.
  • StartRead – Enable status readback during a write.
  • EWD – Enable watchdog timer.
  • WD Period – Select the timeout period for the watchdog timer.
  • ShtCctLim – Programmable short-circuit limit on the VOUT_x pin in the event of a short-circuit condition.
  • OutEn All – Enables the output on all four DACs simultaneously.
  • DC-DC All – Powers up the dc-to-dc converter on all four channels simultaneously.

Section H is used to write data into the Slew Rate Control Register.

Options:

  • SE – Enable SE.
  • SR Clock – Slew Rate Update Clock Options.
  • SR Step – Slew Rate Step Size Options.

Section I is used to write data into the Software Register.

Options:

  • User Bit – This bit is mapped to Bit D11 of the status register.
  • Software Reset – Performs a reset of the AD5755.

Troubleshooting

In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues:

  • Check that the evaluation board is powered as instructed in the board's user guide.
  • In uC-Probe refresh the symbols file by right-clicking on the System Browser window and selecting Refresh Symbols.
  • If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.

More information

resources/fpga/xilinx/interposer/ad5755.1329497250.txt.gz · Last modified: 17 Feb 2012 17:47 by adrianc