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—resources:fpga:xilinx:interposer:ad5755 [28 May 2012 15:44] – Approved Alexandru.Tofan
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 +====== AD5755 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design ======
  
 +
 +===== Supported Devices =====
 +
 +  * [[adi>AD5755]]
 +  * [[adi>AD5755-1]]
 +
 +===== Evaluation Boards =====
 +
 +  * [[adi>EVAL-AD5755SDZ]]
 +  * [[adi>EVAL-AD5755-1SDZ]]
 +
 +====== Overview ======
 +
 +This document presents the steps to setup an environment for using the **[[adi>AD5755|EVAL-AD5755SDZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5755SDZ Evaluation Board with the Xilinx KC705 board.
 +
 +{{ :resources:fpga:xilinx:interposer:img_ad5755.jpg }}
 +
 +For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a:
 +  * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)**
 +  * a compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]]
 +  * corresponding PC software
 +The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software.  Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.
 +
 +Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5755SDZ** Evaluation Board.
 +
 +{{ :resources:fpga:altera:bemicro:ad5755_sdp1z.png?400 }}
 +
 +The [[adi>AD5755]] is a quad, voltage and current output DAC that operates with a power supply range from -26.4 V to +33 V. On-chip dynamic power control minimizes package power dissipation in current mode. This is achieved by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on chip power dissipation. For AD5755-1, each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output.
 +
 +The **EVAL-AD5755SDZ** evaluation board is designed to help customers quickly prototype new AD5755 circuits and reduce design time. To power the AD5755SDZ evaluation board supply +/-15V between the AVSS (-15V) and AVDD (+15V) inputs for the analog supply and 5V between PGND(0V) and AVCC(+5V) as DC-to-DC supply voltage.
 +
 +===== More information =====
 +  * [[adi>AD5755|AD5755 Product Info]] - pricing, samples, datasheet
 +  * [[adi>/static/imported-files/user_guides/UG-244.pdf|EVAL-AD5755SDZ evaluation board user guide]]
 +  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
 +  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]]
 +
 +====== Getting Started ======
 +
 +The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
 +
 +===== Required Hardware =====
 +
 +  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
 +  * FMC-SDP adapter board
 +  * **EVAL-AD5755** evaluation board
 +
 +===== Required Software =====
 +
 +  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
 +  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool
 +
 +===== Downloads =====
 +
 +  * {{:resources:fpga:xilinx:interposer:ad5755_evalboard.zip|Reference Design Files}}
 +
 +The following table presents a short description the reference design archive contents.
 +
 +^ **Folder** ^ **Description** ^
 +| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. |
 +| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. |
 +| Software | Contains the source files of the software project that will be run by the Microblaze processor.|
 +| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. |
 +
 +====== Run the Demonstration Project ======
 +
 +{{page>ucprobe_common}}
 +
 +===== Demonstration Project User Interface =====
 +
 +The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5755SDZ** evaluation board.
 +
 +{{ :resources:fpga:altera:bemicro:ad5755_interface.png?700 }}
 +
 +**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board.
 +
 +**Section B** is used to select the DAC channel.
 +
 +**Section C** is used to write data into the register selected by the Selection Slider.
 +
 +Options:
 +
 +  * Write to DAC data register (individual channel write).
 +  * Write to gain register (individual channel write).
 +  * Write to gain register (all DACs).
 +  * Write to offset register (individual channel write).
 +  * Write to offset register (all DACs) .
 +  * Write to clear code register (individual channel write).
 +
 +**Section D** is used to read data from the register selected by the Selection Slider.
 +
 +Options:
 +
 +  * Read from DAC data register (individual channel read).
 +  * Read from DAC control register (individual channel read).
 +  * Read from Gain register (individual channel read).
 +  * Read from Offset register (individual channel read).
 +  * Read from Clear Code register (individual channel read).
 +  * Read from Slew Rate control register (individual channel read).
 +  * Read from Status register.
 +  * Read from Main control register.
 +  * Read from DC-to-DC control register.
 +
 +**Section E** is used to write data into the DAC n Control Register.
 +
 +Options:
 +
 +  * Internal – Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel.
 +  * Clear – Clear enable bit.
 +  * Output – Enables/disables the selected output channel.
 +  * Rset – Selects an internal or external current sense resistor for the selected DAC channel.
 +  * DC-DC – Powers the dc-to-dc converter on the selected channel.
 +  * OVRNG – Enables 20% overrange on voltage output channel only. No current output overrange available.
 +  * Output Range – Selects the output range to be enabled.
 +
 +**Section F** is used to write data into the DC-DC Control Register.
 +
 +Options:
 +
 +  * DC-DC Comp – Selects between an internal and external compensation resistor for the dc-to-dc converter.
 +  * Phase – User programmable dc-to-dc converter phase (between channels).
 +  * Frequency – DC-to-dc switching frequency.
 +  * Max Voltage – Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter.
 +
 +**Section G** is used to write data into the Main Control Register.
 +
 +Options:
 +
 +  * POC – The POC bit determines the state of the voltage output channels during normal operation.
 +  * StartRead – Enable status readback during a write.
 +  * EWD – Enable watchdog timer.
 +  * WD Period – Select the timeout period for the watchdog timer.
 +  * ShtCctLim – Programmable short-circuit limit on the VOUT_x pin in the event of a short-circuit condition.
 +  * OutEn All – Enables the output on all four DACs simultaneously.
 +  * DC-DC All – Powers up the dc-to-dc converter on all four channels simultaneously.
 +
 +**Section H** is used to write data into the Slew Rate Control Register.
 +
 +Options:
 +
 +  * SE – Enable SE.
 +  * SR Clock – Slew Rate Update Clock Options.
 +  * SR Step – Slew Rate Step Size Options.
 +
 +**Section I** is used to write data into the Software Register.
 +
 +Options:
 +
 +  * User Bit – This bit is mapped to Bit D11 of the status register.
 +  * Software Reset – Performs a reset of the AD5755.
 +
 +===== Troubleshooting =====
 +
 +In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues:
 +  * Check that the evaluation board is powered as instructed in the board's user guide.
 +  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**.
 +  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.
 +
 +====== More information ======
 +  * [[resources:tools-software:linux-drivers:iio-dac:ad5755|AD5755 IIO DAC Linux Driver]]
 +{{page>ez_common}}
resources/fpga/xilinx/interposer/ad5755.txt · Last modified: 09 Jan 2021 00:48 by Robin Getz

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