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resources:fpga:xilinx:interposer:ad5755 [28 Sep 2012 11:23] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina | resources:fpga:xilinx:interposer:ad5755 [22 Jul 2019 13:44] – Update no-OS driver link Andrei Drimbarean | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
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* [[adi>/ | * [[adi>/ | ||
* [[http:// | * [[http:// | ||
- | * [[http:// | ||
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). |
- | * [[http:// | + | * UART Terminal (Tera Term/Hyperterminal), |
===== Downloads ===== | ===== Downloads ===== | ||
+ | <WRAP round download 80%> | ||
+ | \\ | ||
+ | * **AD5755 Driver:** https:// | ||
+ | * **AD5755 Commands:** https:// | ||
+ | * **Xilinx Boards Common Drivers:** https:// | ||
+ | * **EDK KC705 Reference project:** https:// | ||
+ | \\ | ||
+ | </ | ||
- | * {{: | + | ===== Hardware setup ===== |
- | The following table presents a short description | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting | ||
+ | </ | ||
- | ^ **Folder** ^ **Description** ^ | + | |
- | | Bit | Contains | + | * Connect |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | |
- | | Software | Contains the source files of the software project that will be run by the Microblaze processor.| | + | |
- | | uCProbeInterface | Contains | + | |
- | ====== Run the Demonstration Project ====== | + | <WRAP round important 80%> |
+ | \\ | ||
+ | To power on the EVAL-AD5755 evaluation board, you need to provide an external +15V AVdd and -15V AVss analog supply voltage and a +5V AVcc DC-to-DC supply voltage, which will supplies all four on-board dc-to-dc blocks and may draw as much as 0.8 A peak current per channel (for more information see: [[adi>/ | ||
+ | </ | ||
- | {{page> | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented in this version of EVAL-AD5755 reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **register=** | Writes to the a data register. Accepted values:\\ **Register address: | ||
+ | | **control=** | Writes to the a control register. Accepted values:\\ **Register address: | ||
+ | | **register? | ||
+ | | **power=** | Set the power state of the dc-to-dc converters, DAC and internal amplifiers for the selected channel. Accepted values:\\ **Channel: | ||
+ | | **power?** | Displays the power state of the dc-to-dc converters, | ||
+ | | **range=** | Set the range of the selected channel. Accepted values:\\ **Channel: | ||
+ | | **range?** | Displays the range of the selected channel. Accepted values: \\ **Channel: | ||
+ | | **voltage=** | Sets the output voltage for a selected channel. Accepted values: \\ **Channel: | ||
+ | | **voltage? | ||
+ | | **current=** | Displays the output current for a selected channel. Accepted values: \\ **Channel: | ||
+ | | **current? | ||
+ | | **getStatus!** | Read back the Status register and print any faults or errors. | | ||
+ | | **testSPI!** | Ensure that the SPI interface are working correctly. | | ||
+ | |||
+ | Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. | ||
- | ===== Demonstration Project User Interface ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5755SDZ** evaluation board. | + | ===== Software Project Setup ===== |
- | + | {{page> | |
- | {{ : | + | |
- | + | ||
- | **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **// | + | |
- | + | ||
- | **Section B** is used to select the DAC channel. | + | |
- | + | ||
- | **Section C** is used to write data into the register selected by the Selection Slider. | + | |
- | + | ||
- | Options: | + | |
- | + | ||
- | * Write to DAC data register (individual channel write). | + | |
- | * Write to gain register (individual channel write). | + | |
- | * Write to gain register (all DACs). | + | |
- | * Write to offset register (individual channel write). | + | |
- | * Write to offset register (all DACs) . | + | |
- | * Write to clear code register (individual channel write). | + | |
- | + | ||
- | **Section D** is used to read data from the register selected by the Selection Slider. | + | |
- | + | ||
- | Options: | + | |
- | + | ||
- | * Read from DAC data register (individual channel read). | + | |
- | * Read from DAC control register (individual channel read). | + | |
- | * Read from Gain register (individual channel read). | + | |
- | * Read from Offset register (individual channel read). | + | |
- | * Read from Clear Code register (individual channel read). | + | |
- | * Read from Slew Rate control register (individual channel read). | + | |
- | * Read from Status register. | + | |
- | * Read from Main control register. | + | |
- | * Read from DC-to-DC control register. | + | |
- | + | ||
- | **Section E** is used to write data into the DAC n Control Register. | + | |
- | + | ||
- | Options: | + | |
- | + | ||
- | * Internal – Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. | + | |
- | * Clear – Clear enable bit. | + | |
- | * Output – Enables/ | + | |
- | * Rset – Selects an internal or external current sense resistor for the selected DAC channel. | + | |
- | * DC-DC – Powers the dc-to-dc converter on the selected channel. | + | |
- | * OVRNG – Enables 20% overrange on voltage output channel only. No current output overrange available. | + | |
- | * Output Range – Selects the output range to be enabled. | + | |
- | + | ||
- | **Section F** is used to write data into the DC-DC Control Register. | + | |
- | + | ||
- | Options: | + | |
- | + | ||
- | * DC-DC Comp – Selects between an internal and external compensation resistor for the dc-to-dc converter. | + | |
- | * Phase – User programmable dc-to-dc converter phase (between channels). | + | |
- | * Frequency – DC-to-dc switching frequency. | + | |
- | * Max Voltage – Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter. | + | |
- | + | ||
- | **Section G** is used to write data into the Main Control Register. | + | |
- | + | ||
- | Options: | + | |
- | + | ||
- | * POC – The POC bit determines the state of the voltage output channels during normal operation. | + | |
- | * StartRead – Enable status readback during a write. | + | |
- | * EWD – Enable watchdog timer. | + | |
- | * WD Period – Select the timeout period for the watchdog timer. | + | |
- | * ShtCctLim – Programmable short-circuit limit on the VOUT_x pin in the event of a short-circuit condition. | + | |
- | * OutEn All – Enables the output on all four DACs simultaneously. | + | |
- | * DC-DC All – Powers up the dc-to-dc converter on all four channels simultaneously. | + | |
- | + | ||
- | **Section H** is used to write data into the Slew Rate Control Register. | + | |
- | + | ||
- | Options: | + | |
- | + | ||
- | * SE – Enable SE. | + | |
- | * SR Clock – Slew Rate Update Clock Options. | + | |
- | * SR Step – Slew Rate Step Size Options. | + | |
- | + | ||
- | **Section I** is used to write data into the Software Register. | + | |
- | + | ||
- | Options: | + | |
- | + | ||
- | * User Bit – This bit is mapped to Bit D11 of the status register. | + | |
- | * Software Reset – Performs a reset of the AD5755. | + | |
- | + | ||
- | ===== Troubleshooting | + | |
- | + | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | |
- | * Check that the evaluation board is powered as instructed in the board' | + | |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
* [[resources: | * [[resources: | ||
{{page> | {{page> |