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--- resources:fpga:xilinx:interposer:ad5694r [03 Jan 2013 20:42]
external edit
+++ resources:fpga:xilinx:interposer:ad5694r [09 Jan 2021 00:48] (current)
Robin Getz user interwiki links
@@ Line 12: / Line 12: @@
 ====== Overview ======
-This document presents the steps to setup an environment for using the **[[adi>AD5694R|EVAL-AD5694RSDZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5694RSDZ Evaluation Board with the Xilinx KC705 board.
+This document presents the steps to setup an environment for using the **[[adi>AD5694R|EVAL-AD5694RSDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5694RSDZ Evaluation Board with the Xilinx KC705 board.
 {{ :resources:fpga:xilinx:interposer:img_ad5694r.jpg?400 }}
@@ Line 29: / Line 29: @@
   * [[adi>AD5694R|AD5694R Product Info]] - pricing, samples, datasheet
   * EVAL-AD5694RSDZ evaluation board user guide
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]]
 ====== Getting Started ======
@@ Line 38: / Line 37: @@
 ===== Required Hardware =====
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
   * FMC-SDP adapter board
   * **EVAL-AD5694R** evaluation board
@@ Line 44: / Line 43: @@
 ===== Required Software =====
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
+  * Xilinx ISE 14.6.
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool
+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200.
+  * The EVAL-AD5694R reference project for Xilinx KC705 FPGA.
 ===== Downloads =====
+<WRAP round download 80%>
-  * {{:resources:fpga:xilinx:interposer:ad5694r_evalboard.zip|Reference Design Files}}
+\\
+  * **AD5694R Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5686
-The following table presents a short description the reference design archive contents.
+  * **AD5694R Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5686
+  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common
-^ **Folder** ^ **Description** ^
+  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. |
+\\
-| Microblaze | Contains the EDK project for the Microblaze softcore that will be implemented in the KC705 FPGA. |
+</WRAP>
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.|
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. |
 ====== Run the Demonstration Project ======
-===== Hardware Setup =====
+===== Hardware setup =====
-<WRAP important>Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.</WRAP>
+<WRAP round important 80%>
+\\
+Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
+</WRAP>
   * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
   * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
-  * Start IMPACT, and double click “//Boundary Scan//”. Right click and select //Initialize Chain//. The program should recognize the Kintex 7 device (see screenshot below).
-{{ :resources:fpga:xilinx:interposer:impact_config.png?300 }}
-  * Program the KC705 FPGA using the "//Bit/download.bit//" file provided in the reference design archive.
-  * Power the ADI evaluation board.
-At this point everything is set up and it is possible to start the evaluation of the ADI hardware through the controls in the uC-Probe application provided in the reference design.
-===== Configure uC-Probe =====
-Launch **uC-Probe** from the **//Start -> All Programs -> Micrium -> uC-Probe//**.
-Select **uC-Probe** options.
-  * Click on the **uC-Probe** icon on the top left portion of the screen.
-  * Click on the **//Options//** button to open the dialog box.
-{{ :resources:fpga:altera:bemicro:ucprobeoptionsbtn.png?300 }}
-Set target board communication protocol as **//RS-232//**
-  * Click on the **//Communication//** tab icon on the top left portion of the dialog box
-  * Select the **//RS-232//** option.
-{{ :resources:fpga:xilinx:interposer:ucprobe_comm.png?300 }}
-Setup **//RS-232//** communication settings
-  * Select the **//RS-232//** option from the **//Communication//** tab.
-  * Select the COM port to which the KC705 board is connected.
-  * Set the Baud Rate to 115200 bps.
-{{ :resources:fpga:xilinx:interposer:ucprobe_rs232.png?300 }}
-  * Press **//Apply//** and **//OK//** to exit the options menu.
-===== Load and Run the Demonstration Project =====
-  * Click the **//Open//** option from the **uC-Probe** menu and select the file **//ucProbeInterface/AD5694R_Interface.wsp//** provided within the reference design files.
-  * Before opening the interface **uC-Probe** will ask for a symbols file that must be associated with the interface. Select the file **//ucProbeInterface/ADIEvalBoard.elf//** to be loaded as a symbol file.
-  * Run the demonstration project by pressing the **//Play//** button.
-{{ :resources:fpga:altera:bemicro:image081.png?200 }}
-<WRAP tip>In some cases it is possible that the uC-Probe interface will not respond to the commands the first time it is ran. In this situation just stop the interface by pressing the **//Stop//** button and run it again by pressing the **//Play//** button.</WRAP>
-===== Demonstration Project User Interface =====
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5694RSDZ** evaluation board.
-{{ :resources:fpga:altera:bemicro:ad5694r_interface.png?700 }}
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the //ON/OFF// switch. The //Activity// LED turns green when the communication is active. If the //ON/OFF// switch is set to //ON// and the //Activity// LED is //BLACK// it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems.
-**Section B** is used to select the //Command// to be sent to the DAC. The definition of each command is available in Table 7 of the part's datasheet.
-**Section C** is used to select the //Address// of the registers to be affected by the command, if the command is 1, 2 or 3. If the selected command is 5, the //Address// buttons will be used to program the //LDAK MASK REGISTER// for the corresponding DAC. For the other commands, they are ignored.
-**Section D** is used to program the value to be written to the DAC registers.
-**Section E** is used to send the selected command to the DAC.
-**Section F** is used to configure the databits sent for the command 4. Each DAC's power operation can be configured independently.
+<WRAP round important 80%>
+\\
+To power on the EVAL-AD5694R evaluation board, you need to apply +6V supply voltage to J3 connector of the board.
+</WRAP>
-**Section G** is used to configure the databits sent for the command 7. If the button is pressed, the Internal reference will be turned off.
+===== Reference Project Overview =====
+The following commands were implemented in this version of EVAL-AD5694R reference project for Xilinx KC705 FPGA board.
+^ Command ^ Description ^
+| **help?** | Displays all available commands. |
+| **reset!** | Activate a power-on reset. |
+| **load=** | Loads selected DAC input register with a given value. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ value:\\ 0 .. 4095 - value to be written in register. |
+| **update=** | Update the selected DAC channel with the input register. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ 4 - select all channels. |
+| **loadAndUpdate=** | Loads and updates the selected DAC with a given value. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ value:\\ 0 .. 4095 - value to be written in register. |
+| **pwrMode=** | Set up the Power Mode of a selected channel. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ 4 - select all channels.\\ power mode:\\ 0 - normal operation.\\ 1 - 1KOhm to GND.\\ 2 - 100KOhms to GND.\\ 3 - three-state. |
+| **pwrMode?** | Displays the power mode for one selected DAC. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D. |
+| **ldacMask=** | Set up the LDAC mask register. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ 4 - select all channels.\\ set/reset mask:\\ 0 - reset LDAC mask for the selected channel.\\ 1 - set LDAC mask for the selected channel. |
+| **ldacMask?** | Displays the LDAC register. |
+| **intRef=** | Turns ON or OFF the internal reference. Accepted values:\\ 0 - turns OFF the internal reference.(default)\\ 1 - turns ON the internal reference. |
+| **intRef?** | Displays the status of the internal reference. |
+| **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. |
+| **ldacPin?** | Displays the value of LDAC pin. |
-**Section H** is used to control the Hardware pins of the AD7694R.
-**Section I** is used to perform a readback of all four registers of AD7694R.
+Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
-===== Troubleshooting =====
+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral.
+{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }}
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues:
+===== Software Project Setup =====
-  * Check that the evaluation board is powered as instructed in the board's user guide.
+{{page>import_workspace}}
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**.
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.
 ====== More information ======
 {{page>ez_common}}

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