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AD5668 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design

Supported Devices

Evaluation Boards


This document presents the steps to setup an environment for using the EVAL-AD5668SDZ evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the Micrium µC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-AD5668SDZ Evaluation Board with the Xilinx KC705 board.


For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:

  • 1. A controller board like the SDP-B ( EVAL-SDP-CS1Z)
  • 2. The component SDP compatible product evaluation board
  • 3. Corresponding PC software ( shipped with the product evaluation board)

The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.

Note: it is expected that the analog performance on the two platforms may differ.

28 Sep 2012 10:32 · AdrianC

Below is presented a picture of SDP-B Controller Board with the EVAL-AD5668SDZ Evaluation Board.

The EVAL-AD5668EBZ / AD5668SD_Z evaluation board is a member of a growing number of boards available for the SDP. Designed to help customers evaluate performance or quickly prototype new AD5668 circuits and reduce design time, the EVAL-AD5668EBZ / AD5668SD_Z evaluation board can operate from a single 2.7 V to 5.5 V supply. The part incorporates an internal 1.25 V or 2.5 V on-board reference to give an output voltage span of 2.5 V or 5 V, respectively. The on-board reference is off at power-up allowing for the use of an external reference; the REF195 is used on this evaluation board. The AD5668 must be written to after power-up to turn on the internal reference.

The AD5668 is a low power, octal, 16-bit, buffered voltage-output DAC. The device operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. The AD5668 has an on-chip reference with an internal gain of 2. The AD5668-1 has an 1.25 V 5 ppm/°C reference, giving a full-scale output range of 2.5 V; the AD5668-2, -3 has a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V. The on-board reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write. The AD5668 utilizes a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The on-chip precision output amplifier enables rail-to-rail output swing.

More information

Getting Started

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

Required Hardware

Required Software

  • Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
  • uC-Probe run-time monitoring tool


The following table presents a short description the reference design archive contents.

Folder Description
Bit Contains the KC705 configuration file that can be used to program the system for quick evaluation.
Microblaze Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA.
Software Contains the source files of the software project that will be run by the Microblaze processor.
uCProbeInterface Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory.

Run the Demonstration Project

Hardware Setup

Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.

  • Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
  • Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  • Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Kintex 7 device (see screenshot below).

  • Program the KC705 FPGA using the “Bit/download.bit” file provided in the reference design archive.
  • Power the ADI evaluation board.

At this point everything is set up and it is possible to start the evaluation of the ADI hardware through the controls in the uC-Probe application provided in the reference design.

Configure uC-Probe

Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.

Select uC-Probe options.

  • Click on the uC-Probe icon on the top left portion of the screen.
  • Click on the Options button to open the dialog box.

Set target board communication protocol as RS-232

  • Click on the Communication tab icon on the top left portion of the dialog box
  • Select the RS-232 option.

Setup RS-232 communication settings

  • Select the RS-232 option from the Communication tab.
  • Select the COM port to which the KC705 board is connected.
  • Set the Baud Rate to 115200 bps.

  • Press Apply and OK to exit the options menu.

Load and Run the Demonstration Project

  • Click the Open option from the uC-Probe menu and select the .wsp file from the ucProbeInterface folder provided within the reference design files.
  • Before opening the interface uC-Probe will ask for a symbols file that must be associated with the interface. Select the file ucProbeInterface/ADIEvalBoard.elf to be loaded as a symbol file.
  • Run the demonstration project by pressing the Play button.

  • In some cases it is possible that the uC-Probe interface will not respond to the commands the first time it is ran. In this situation just stop the interface by pressing the Stop button and run it again by pressing the Play button.
  • After starting the uC-Probe interface wait until the status of the connection with the board displayed on the bottom of the screen is set to Connected. It is possible to use the interface only after the status is changed to Connected and the data transfer speed displayed next to the connection status is different than 0.
16 Feb 2012 09:23 · acozma

Demonstration Project User Interface

The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-AD5668EBZ / AD5668SD_Z evaluation board.

Section A is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board. See the Troubleshooting section for indications on how to fix the communication problems.

Section B is used to set the output value on the DAC channels. In order to use this functionality, one should select the channel, select the data bits and press the Set on DAC switch. If the LED is active, the value will be continuously updated on the DAC. The DAC may have different reference voltages, so the user should select the value of the reference currently used. Based on this voltage, the output voltage corresponding to the data bits will be displayed.

Section C is used to send any command to the AD5668. The command list is available in table “Command Definitions” from the datasheet. Using the sliders, the command, address and databits to be sent should be configured. After that, Send command to DAC switch should be activated. There are two sliders used for setting the Value, one for large values and one for small values.

For command 4, Power down/power up DAC, the Channel value is used to select the power down mode: 0 for normal operation, 1 for 1k to GND, 2 for 100k to GND and 3 for Three-state operation. The least significant eight bits from the Value are used for channel selection. For additional information see datasheet.

For command 5, Load clear code register, the last two bits from value parameter are used as Clear code register bits. 0 will load the clear registers with 0x0000, 1 will load them with 0x8000, 2 will load them with 0xFFFF and 3 is used for no operation.

For command 6, Load LDAC register, the least significant eight bits from the value are used for channel selection. If 1, the channel will consider always the LDAC active.

For command 7, Reset, the value and channel parameters are not important.

For command 8, Set up internal REF register, the last bit from Value is used for reference selection (0 internal reference off, other than 0 internal reference on).

Section D is used to toggle the hardware pins. The functionality of the pins is described in the datasheet, table “Pin Function Descriptions”. When pressing the Toggle \LDAC switch, a HIGH to LOW and a LOW to HIGH transition will be initiated on the LDAC pin. The DAC registers will be updated with the input registers data. When pressing the Toggle \CLR switch, a HIGH to LOW and a LOW to HIGH transition will be initiated on the CLR pin. This will update the Input registers and DAC registers with the data contained in the CLR code register: zero, midscale or full scale. Default settings clear the output to 0.

Section E is used to for configuring the ADC. It is possible that the ADC to be supplied with a different voltage than the reference voltage used for the DAC case in which ADC Supply should be correctly configured by the user. Activating the Continuous loop button, the ADC will read continuously sequentially all eight channels from the DAC. If it is not active, the ADC will only read the channel selected in section B. The voltage is computed based on the ADC Supply configuration.


In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues:

  • Check that the evaluation board is powered as instructed in the board's user guide.
  • In uC-Probe refresh the symbols file by right-clicking on the System Browser window and selecting Refresh Symbols.
  • If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.

More information

28 May 2012 15:18
resources/fpga/xilinx/interposer/ad5668.1348823941.txt.gz · Last modified: 28 Sep 2012 11:19 by AdrianC