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resources:fpga:xilinx:interposer:ad5668 [28 Sep 2012 11:19] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina | resources:fpga:xilinx:interposer:ad5668 [01 Oct 2013 09:35] – changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact Lucian Sin | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
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* [[adi>/ | * [[adi>/ | ||
* [[http:// | * [[http:// | ||
- | * [[http:// | ||
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD5668 reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **AD5668 Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **AD5668 Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | + | ||
- | ===== Demonstration Project User Interface | + | |
- | + | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5668EBZ / AD5668SD_Z** evaluation board. | + | |
- | + | ||
- | {{ : | + | |
- | + | ||
- | **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **ON/OFF** switch. The **Activity** LED turns green when the communication is active. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. | + | |
- | + | ||
- | **Section B** is used to set the output value on the DAC channels. In order to use this functionality, | + | |
- | + | ||
- | **Section C** is used to send any command to the AD5668. The command list is available in table " | + | |
- | There are two sliders used for setting the Value, one for large values and one for small values. | + | |
- | + | ||
- | For command 4, **Power down/power up DAC**, the Channel value is used to select the power down mode: 0 for normal operation, 1 for 1k to GND, 2 for 100k to GND and 3 for Three-state operation. The least significant eight bits from the Value are used for channel selection. For additional information see [[adi> | + | |
- | + | ||
- | For command 5, **Load clear code register**, the last two bits from value parameter are used as Clear code register bits. 0 will load the clear registers with 0x0000, 1 will load them with 0x8000, 2 will load them with 0xFFFF and 3 is used for no operation. | + | |
- | + | ||
- | For command 6, **Load LDAC register**, the least significant eight bits from the value are used for channel selection. If 1, the channel will consider always the LDAC active. | + | |
- | For command 7, **Reset**, | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change | ||
+ | </ | ||
- | For command 8, **Set up internal REF register**, | + | |
+ | | ||
- | **Section D** is used to toggle the hardware pins. The functionality of the pins is described in the [[adi>ad5668|datasheet]], | + | <WRAP round important 80%> |
- | When pressing the **Toggle | + | \\ |
- | When pressing the **Toggle \CLR** switch, a HIGH to LOW and a LOW to HIGH transition will be initiated | + | To power on the EVAL-AD5668 evaluation board, you need to provide +5V supply voltage |
+ | </ | ||
- | **Section E** is used to for configuring | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented in this version of EVAL-AD5668 reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **reset!** | Makes a power-on reset. | | ||
+ | | **powerMode=** | Selects a given power mode for selected DAC. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ power mode:\\ 0 - normal operation.\\ 1 - 1KOhm to GND.\\ 2 - 100KOhms to GND.\\ 3 - three-state. | | ||
+ | | **powerMode? | ||
+ | | **intRef=** | Turns on/ | ||
+ | | **intRef?** | Displays | ||
+ | | **loadN=** | Loads selected | ||
+ | | **updateN** | Updates | ||
+ | | **loadNUpdateN** | Loads and updates | ||
+ | | **loadNUpdateAll** | Loads the selected DAC with a given value and updates | ||
+ | | **enLdacPin=** | Enables/ | ||
+ | | **enLdacPin? | ||
+ | | **clrCode=** | Loads Clear Code Register with specific clear code.\\ Accepted values:\\ 0 - clears code to zero scale when CLR pin goes from high to low.\\ 1 - clears code to midscale when CLR pin goes from high to low.\\ 2 - clears code to full scale when CLR pin goes from high to low.\\ 3 - no operation. | | ||
+ | | **clrCode? | ||
+ | | **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. | | ||
+ | | **ldacPin? | ||
+ | | **clrPin=** | Sets the output value of CLR pin. Accepted values:\\ 0 - sets CLR pin low.\\ 1 - sets CLR pin high.(default) | | ||
+ | | **clrPin?** | Displays | ||
- | ===== Troubleshooting ===== | + | Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. |
- | In case there is a communication problem with the board the follwing actions can be perfomed | + | The following image shows a generic list of commands |
- | * Check that the evaluation board is powered as instructed in the board' | + | {{ : |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. | + | ===== Software Project Setup ===== |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | {{page> |
====== More information ====== | ====== More information ====== | ||
{{page> | {{page> |