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resources:fpga:xilinx:interposer:ad5541a [28 Sep 2012 10:50] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina | resources:fpga:xilinx:interposer:ad5541a [09 Jan 2021 00:48] (current) – user interwiki links Robin Getz | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
Line 29: | Line 29: | ||
* [[adi> | * [[adi> | ||
* {{resources: | * {{resources: | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
- | * [[http:// | + | |
====== Getting Started ====== | ====== Getting Started ====== | ||
- | The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation | + | The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the reference |
===== Required Hardware ===== | ===== Required Hardware ===== | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
* FMC-SDP adapter board | * FMC-SDP adapter board | ||
- | * **EVAL-AD5541A** evaluation board | + | * **EVAL-AD5541ASDZ** evaluation board |
===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD5541A reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **AD5541A Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **AD5541A Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | ===== Demonstration Project User Interface ===== | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. | ||
+ | </ | ||
- | The following figure presents | + | * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. |
+ | | ||
- | {{ :resources:fpga:altera: | + | <WRAP round important 80%> |
+ | \\ | ||
+ | The EVAL-AD5542A evaluation board will be powered from PCs USB interface (LK8 position=A, LK9 position=B, LK7 position=B, LK3 position=A, LK2 position=A). | ||
+ | </ | ||
+ | ===== Reference Project Overview ===== | ||
+ | The following commands were implemented in this version of EVAL-AD5541A reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **register=** | Writes to the DAC register. Accepted values:\\ 0 .. 65535 - the value written to the DAC. | | ||
+ | | **register? | ||
+ | | **voltage=** | Sets the DAC output voltage. Accepted values:\\ 0 .. +2500 - desired output voltage in milivolts. | | ||
+ | | **voltage? | ||
+ | | **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. | | ||
+ | | **ldacPin?** | Displays the value of LDAC pin. | | ||
- | * The communication with the board is activated / deactivated by toggling the **// | + | Commands can be executed using a serial terminal connected |
- | * The **//DAC//** switch is used to enable/ | + | |
- | * The **// | + | |
- | * The **//DAC Value//** slider is used to set the value to be loaded into the DAC register. The selected value is displayed in the numeric box next to the slider. | + | |
- | ===== Troubleshooting ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | ===== Software Project Setup ===== |
- | * Check that the evaluation board is powered as instructed in the board' | + | {{page> |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
* [[resources: | * [[resources: | ||
{{page> | {{page> |