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resources:fpga:xilinx:interposer:ad5415 [06 Sep 2013 15:47] – added link to EDK KC705 reference project on Github Lucian Sinresources:fpga:xilinx:interposer:ad5415 [09 Jan 2021 00:48] (current) – user interwiki links Robin Getz
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 ===== Evaluation Boards ===== ===== Evaluation Boards =====
  
-  * [[adi>EVAL-AD5415SDZ]]+  * [[adi>EVAL-AD5415|EVAL-AD5415SDZ]]
  
 ====== Overview ====== ====== Overview ======
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   * [[adi>AD5415|AD5415 Product Info]] - pricing, samples, datasheet   * [[adi>AD5415|AD5415 Product Info]] - pricing, samples, datasheet
   * [[adi>/static/imported-files/user_guides/UG-296.pdf|EVAL-AD5415SDZ evaluation board user guide]]   * [[adi>/static/imported-files/user_guides/UG-296.pdf|EVAL-AD5415SDZ evaluation board user guide]]
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Hardware ===== ===== Required Hardware =====
  
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
   * FMC-SDP adapter board   * FMC-SDP adapter board
   * **EVAL-AD5415** evaluation board   * **EVAL-AD5415** evaluation board
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 <WRAP round download 80%> <WRAP round download 80%>
 \\ \\
-  * {{:resources:fpga:xilinx:interposer:cf_ad5415_kc705.zip|Reference Design Files}} +  * **AD5415 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5449 
-  * **AD5415 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5415 +  * **AD5415 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5449
-  * **AD5415 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5415+
   * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common   * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common
   * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705   * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705
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 To power on the EVAL-AD5415 evaluation board, you need to provide external +12V VDD and -12V VSS supply voltage used to power the output amplifier (for more information see: [[adi>/static/imported-files/user_guides/UG-296.pdf|EVAL-AD5415SDZ evaluation board user guide]]) and a +5V supply used to power the DAC and transceivers. To power on the EVAL-AD5415 evaluation board, you need to provide external +12V VDD and -12V VSS supply voltage used to power the output amplifier (for more information see: [[adi>/static/imported-files/user_guides/UG-296.pdf|EVAL-AD5415SDZ evaluation board user guide]]) and a +5V supply used to power the DAC and transceivers.
 </WRAP> </WRAP>
- 
-===== Quick start evaluation ===== 
-For a quick start evaluation, run the **download.bat** script located in the **SDK/SDK_Workspace/bin** folder provided within the Reference Design Files.  This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR. 
- 
-<WRAP round info 80%> 
-\\ 
-The **download.bat** script assumes that the Xilinx ISE Design Suite 14.6 is installed at this path: **C:/Xilinx/14.6**. If the installation path on your computer is different, please modify the script accordingly. 
-</WRAP> 
- 
-If programming was successful, you should be seeing the command messages appear on the terminal. 
  
 ===== Reference Project Overview ===== ===== Reference Project Overview =====
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 | **help?** | Displays all available commands. | | **help?** | Displays all available commands. |
 | **load=** | Loads selected DAC input register with a given value. Accepted values:\\ channel:\\ 0 - select DAC A input register.\\ 1 - select DAC B input register.\\ value:\\ 0 .. 4095 - value to be written in register. | | **load=** | Loads selected DAC input register with a given value. Accepted values:\\ channel:\\ 0 - select DAC A input register.\\ 1 - select DAC B input register.\\ value:\\ 0 .. 4095 - value to be written in register. |
-| **loadBoth=** | Loads both DAC input registers. Accepted values:\\ 0 .. 4095 - value to be written in register. |+| **loadAll=** | Loads both DAC input registers. Accepted values:\\ 0 .. 4095 - value to be written in register. |
 | **loadAndUpdate=** | Loads and updates the selected DAC with a given value. Accepted values:\\ channel:\\ 0 - select DAC A.\\ 1 - select DAC B.\\ value:\\ 0 .. 4095 - value to be written in register. | | **loadAndUpdate=** | Loads and updates the selected DAC with a given value. Accepted values:\\ channel:\\ 0 - select DAC A.\\ 1 - select DAC B.\\ value:\\ 0 .. 4095 - value to be written in register. |
-| **updateBoth!** | Updates both DAC outputs. |+| **updateAll!** | Updates both DAC outputs. |
 | **readback?** | Reads from the selected DAC register. Accepted values:\\ channel:\\ 0 - read from DAC A.\\ 1 - read from DAC B. | | **readback?** | Reads from the selected DAC register. Accepted values:\\ channel:\\ 0 - read from DAC A.\\ 1 - read from DAC B. |
 | **clearToZero!** | Clears both DAC outputs to zero scale. | | **clearToZero!** | Clears both DAC outputs to zero scale. |
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 | **clrPin=** | Sets the output value of CLR pin. Accepted values:\\  | | **clrPin=** | Sets the output value of CLR pin. Accepted values:\\  |
 | **clrPin?** | Displays the value of CLR pin. | | **clrPin?** | Displays the value of CLR pin. |
 +
  
  
resources/fpga/xilinx/interposer/ad5415.1378475258.txt.gz · Last modified: 06 Sep 2013 15:47 by Lucian Sin